Subject: Re: Marvell switch port shows LOWERLAYERDOWN, ping fails

From: Andrew Lunn <[email-masked]>
Date: Wed, 28 Jul 2021 21:24:10 +0200

On Wed, Jul 28, 2021 at 11:33:35AM -0700, Dario Alcocer wrote:
> On 7/28/21 11:23 AM, Andrew Lunn wrote:
> > On Wed, Jul 28, 2021 at 11:07:37AM -0700, Dario Alcocer wrote:
> > > It appears the port link-state issue is caused by the mv88e6xxx switch
> > > driver. The function mv88e6xxx_mac_config identifies the PHY as internal and
> > > skips the call to mv88e6xxx_port_setup_mac.
> > > 
> > > It does not make sense to me why internal PHY configuration should be
> > > skipped.
> > 
> > The switch should do the configuration itself for internal PHYs. At
> > least that works for other switches. What value does CMODE have for
> > the port? 0xf?
> > 
> >      Andrew
> > 
> 
> Is CMODE available via the DSA debugfs? Here are the registers for port0,
> which should be lan1:
> 
> root@dali:~# ls /sys/kernel/debug/dsa/switch0/
> port0/        port1/        port2/        port3/        port4/ port5/
> port6/        tag_protocol  tree
> root@dali:~# ls /sys/kernel/debug/dsa/switch0/port0/
> fdb    mdb    regs   stats  vlan
> root@dali:~# cat /sys/kernel/debug/dsa/switch0/port0/regs
>  0: 100f

It is the lower nibble of this register. So 0xf.

Take a look at:

https://github.com/lunn/mv88e6xxx_dump/blob/master/mv88e6xxx_dump.c

The 1 in 100f means it has found the PHY. But there is no link,
10/Half duplex, etc.

>  1: 0003

This at least looks sensible. Nothing is forced, normal speed
detection should be performed. So what should happen is the link
speed, duplex etc from the internal PHY should directly appear in
register 0. There is no need for software to ask the PHY and then
configure the MAC.

	  Andrew