Subject: Re: [RFC PATCH] net: phy/mdio: enable mmd indirect access through phy_mii_ioctl()

From: "Russell King (Oracle)" <[email-masked]>
Date: Tue, 2 Nov 2021 12:39:52 +0000

On Tue, Nov 02, 2021 at 01:49:42AM +0100, Andrew Lunn wrote:
> > The use of the indirect registers is specific to PHYs, and we already
> > know that various PHYs don't support indirect access, and some emulate
> > access to the EEE registers - both of which are handled at the PHY
> > driver level.
> 
> That is actually an interesting point. Should the ioctl call actually
> use the PHY driver read_mmd and write_mmd? Or should it go direct to
> the bus? realtek uses MII_MMD_DATA for something to do with suspend,
> and hence it uses genphy_write_mmd_unsupported(), or it has its own
> function emulating MMD operations.
> 
> So maybe the ioctl handler actually needs to use __phy_read_mmd() if
> there is a phy at the address, rather than go direct to the bus?
> 
> Or maybe we should just say no, you should do this all from userspace,
> by implementing C45 over C22 in userspace, the ioctl allows that, the
> kernel does not need to be involved.

Yes and no. There's a problem accessing anything that involves some kind
of indirect or paged access with the current API - you can only do one
access under the bus lock at a time, which makes the whole thing
unreliable. We've accepted that unreliability on the grounds that this
interface is for debugging only, so if it does go wrong, you get to keep
all the pieces!

The paged access case is really no different from the indirect C45 case.
They're both exactly the same type of indirect access, just using
different registers.

That said, the MII ioctls are designed to be a bus level thing - you can
address anything on the MII bus with them. Pushing the ioctl up to the
PHY layer means we need to find the right phy device to operate on. What
if we attempt a C45 access at an address that there isn't a phy device?

For example, what would be the effect of trying a C45 indirect access to
a DSA switch?

Personally, my feeling would be that if we want to solve this, we need
to solve this properly - we need to revise the interface so it's
possible to request the kernel to perform a group of MII operations, so
that userspace can safely access any paged/indirect register. With that
solved, there will be no issue with requiring userspace to know what
it's doing with indirect C45 accesses.

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