Subject: Re: [v3 2/2] dsa: mv88e6xxx: make serdes SGMII/Fiber output amplitude configurable

From: Andrew Lunn <[email-masked]>
Date: Wed, 8 Dec 2021 18:55:48 +0100

On Wed, Dec 08, 2021 at 06:36:26PM +0100, Marek Behún wrote:
> On Wed, 8 Dec 2021 19:19:09 +0200
> Vladimir Oltean <[email-masked]> wrote:
> 
> > On Wed, Dec 08, 2021 at 06:00:57PM +0100, Marek Behún wrote:
> > > > Also, maybe drop the "serdes-" prefix? The property will sit under a
> > > > SERDES lane node, so it would be a bit redundant?  
> > > 
> > > Hmm. Holger's proposal adds the property into the port node, not SerDes
> > > lane node. mv88e6xxx does not define bindings for SerDes lane nodes
> > > (yet).  
> > 
> > We need to be careful about that. You're saying that there chances of
> > there being a separate SERDES driver for mv88e6xxx in the future?
> 
> I don't think so. Although Russell is working on rewriting the SerDes
> code to new Phylink API, the SerDes code will always be a part of
> mv88e6xxx driver, I think.

In theory, the 6352 family uses standard c22 layout for its SERDES. It
might be possible to use generic code for that. But given the
architecture, i expect such a change would have the mv88e6xxx
instantiate such generic code, not use an external device.

For the 6390 family the SERDES and the MAC are pretty intertwined, and
it is not a 1:1 mapping. It might be possible to make use of shared
code, but i've much doubt it will be a separate device.

I would put the properties in the port nodes, next to phy-mode,
phy-handle, etc.

Where it might get interesting is the 10G modes, where there are 4
lanes. Is it possible to configure the voltage for each lane? Or is it
one setting for all 4 lanes? I've not looked at the data sheet, so i
cannot answer this.
y
    Andrew