Subject: Re: [PATCH net v2 2/9] net: axienet: Wait for PhyRstCmplt after core reset

From: Andrew Lunn <[email-masked]>
Date: Wed, 12 Jan 2022 20:44:58 +0100

> > Is this bit guaranteed to be clear before you start waiting for it?
> 
> The documentation for the IP core ( 
> https://www.xilinx.com/content/dam/xilinx/support/documentation/ip_documentation/axi_ethernet/v7_2/pg138-axi-ethernet.pdf
>  ) states for the phy_rst_n output signal: "This active-Low reset is held
> active for 10 ms after power is applied and during any reset. After the reset
> goes inactive, the PHY cannot be accessed for an additional 5 ms." The
> PhyRstComplt bit definition mentions "This signal does not transition to 1 for
> 5 ms after PHY_RST_N transitions to 1". Given that a reset of the core has just
> been completed above, the PHY reset should at least have been initiated as
> well, so it should be sufficient to just wait for the bit to become 1 at this
> point.

Great, thanks for checking.

Reviewed-by: Andrew Lunn <[email-masked]>

    Andrew