Subject: Re: [PATCH net-next v2 02/35] dt-bindings: net: Convert FMan MAC bindings to yaml

From: "Russell King (Oracle)" <[email-masked]>
Date: Wed, 29 Jun 2022 15:50:01 +0100

On Tue, Jun 28, 2022 at 06:13:31PM -0400, Sean Anderson wrote:
> This converts the MAC portion of the FMan MAC bindings to yaml.
> 
> Signed-off-by: Sean Anderson <[email-masked]>
> ---
> 
> Changes in v2:
> - New
> 
>  .../bindings/net/fsl,fman-dtsec.yaml          | 144 ++++++++++++++++++
>  .../devicetree/bindings/net/fsl-fman.txt      | 128 +---------------
>  2 files changed, 145 insertions(+), 127 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
> 
> diff --git a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
> new file mode 100644
> index 000000000000..809df1589f20
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
> @@ -0,0 +1,144 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP FMan MAC
> +
> +maintainers:
> +  - Madalin Bucur <[email-masked]>
> +
> +description: |
> +  Each FMan has several MACs, each implementing an Ethernet interface. Earlier
> +  versions of FMan used the Datapath Three Speed Ethernet Controller (dTSEC) for
> +  10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
> +  (10GEC) for 10 Gbit/s speeds. Later versions of FMan use the Multirate
> +  Ethernet Media Access Controller (mEMAC) to handle all speeds.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - fsl,fman-dtsec
> +      - fsl,fman-xgec
> +      - fsl,fman-memac
> +
> +  cell-index:
> +    maximum: 64
> +    description: |
> +      FManV2:
> +      register[bit]           MAC             cell-index
> +      ============================================================
> +      FM_EPI[16]              XGEC            8
> +      FM_EPI[16+n]            dTSECn          n-1
> +      FM_NPI[11+n]            dTSECn          n-1
> +              n = 1,..,5
> +
> +      FManV3:
> +      register[bit]           MAC             cell-index
> +      ============================================================
> +      FM_EPI[16+n]            mEMACn          n-1
> +      FM_EPI[25]              mEMAC10         9
> +
> +      FM_NPI[11+n]            mEMACn          n-1
> +      FM_NPI[10]              mEMAC10         9
> +      FM_NPI[11]              mEMAC9          8
> +              n = 1,..8
> +
> +      FM_EPI and FM_NPI are located in the FMan memory map.
> +
> +      2. SoC registers:
> +
> +      - P2041, P3041, P4080 P5020, P5040:
> +      register[bit]           FMan            MAC             cell
> +                              Unit                            index
> +      ============================================================
> +      DCFG_DEVDISR2[7]        1               XGEC            8
> +      DCFG_DEVDISR2[7+n]      1               dTSECn          n-1
> +      DCFG_DEVDISR2[15]       2               XGEC            8
> +      DCFG_DEVDISR2[15+n]     2               dTSECn          n-1
> +              n = 1,..5
> +
> +      - T1040, T2080, T4240, B4860:
> +      register[bit]                   FMan    MAC             cell
> +                                      Unit                    index
> +      ============================================================
> +      DCFG_CCSR_DEVDISR2[n-1]         1       mEMACn          n-1
> +      DCFG_CCSR_DEVDISR2[11+n]        2       mEMACn          n-1
> +              n = 1,..6,9,10
> +
> +      EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
> +      the specific SoC "Device Configuration/Pin Control" Memory
> +      Map.
> +
> +  reg:
> +    maxItems: 1
> +
> +  fsl,fman-ports:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 2
> +    description: |
> +      An array of two references: the first is the FMan RX port and the second
> +      is the TX port used by this MAC.
> +
> +  ptp-timer:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: A reference to the IEEE1588 timer
> +
> +  pcsphy-handle:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: A reference to the PCS (typically found on the SerDes)

This description includes ethernet-controller.yaml, which contains:

  pcs-handle:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Specifies a reference to a node representing a PCS PHY device on a MDIO
      bus to link with an external PHY (phy-handle) if exists.

Is there a reason why a custom property is needed rather than using the
pcs-handle property already provided by the ethernet-controller DT
description?

Thanks.

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