Subject: Re: [PATCH net-next 3/6] net: dsa: add support for retrieving the interface mode

From: "Russell King (Oracle)" <[email-masked]>
Date: Fri, 15 Jul 2022 23:57:20 +0100

On Sat, Jul 16, 2022 at 01:23:48AM +0300, Vladimir Oltean wrote:
> On Fri, Jul 15, 2022 at 10:31:17PM +0100, Russell King (Oracle) wrote:
> > On Fri, Jul 15, 2022 at 08:24:44PM +0300, Vladimir Oltean wrote:
> > > On Fri, Jul 15, 2022 at 05:01:37PM +0100, Russell King (Oracle) wrote:
> > > > DSA port bindings allow for an optional phy interface mode. When an
> > > > interface mode is not specified, DSA uses the NA interface mode type.
> > > > 
> > > > However, phylink needs to know the parameters of the link, and this
> > > > will become especially important when using phylink for ports that
> > > > are devoid of all properties except the required "reg" property, so
> > > > that phylink can select the maximum supported link settings. Without
> > > > knowing the interface mode, phylink can't truely know the maximum
> > > > link speed.
> > > > 
> > > > Update the prototype for the phylink_get_caps method to allow drivers
> > > > to report this information back to DSA, and update all DSA
> > > > implementations function declarations to cater for this change. No
> > > > code is added to the implementations.
> > > > 
> > > > Reviewed-by: Marek Behún <[email-masked]>
> > > > Signed-off-by: Russell King (Oracle) <[email-masked]>
> > > > ---
> > > (...)
> > > > diff --git a/include/net/dsa.h b/include/net/dsa.h
> > > > index b902b31bebce..7c6870d2c607 100644
> > > > --- a/include/net/dsa.h
> > > > +++ b/include/net/dsa.h
> > > > @@ -852,7 +852,8 @@ struct dsa_switch_ops {
> > > >  	 * PHYLINK integration
> > > >  	 */
> > > >  	void	(*phylink_get_caps)(struct dsa_switch *ds, int port,
> > > > -				    struct phylink_config *config);
> > > > +				    struct phylink_config *config,
> > > > +				    phy_interface_t *default_interface);
> > > 
> > > I would prefer having a dedicated void (*port_max_speed_interface),
> > > because the post-phylink DSA drivers (which are not few) will generally
> > > not need to concern themselves with implementing this, and I don't want
> > > driver writers to think they need to populate every parameter they see
> > > in phylink_get_caps. So the new function needs to be documented
> > > appropriately (specify who needs and who does not need to implement it,
> > > on which ports it will be called, etc).
> > > 
> > > In addition, if we have a dedicated ds->ops->port_max_speed_interface(),
> > > we can do a better job of avoiding breakage with this patch set, since
> > > if DSA cannot find a valid phylink fwnode, AND there is no
> > > port_max_speed_interface() callback for this driver, DSA can still
> > > preserve the current logic of not putting the port down, and not
> > > registering it with phylink. That can be accompanied by a dev_warn() to
> > > state that the CPU/DSA port isn't registered with phylink, please
> > > implement port_max_speed_interface() to address that.
> > 
> > To continue my previous email...
> > 
> > This is a great illustration why posting RFC series is a waste of time.
> > This patch was posted as RFC on:
> > 
> > 24th June
> > 29th June
> > 5th July
> > 13th July
> > 
> > Only when it's been posted today has there been a concern raised about
> > the approach. So, what's the use of asking for comments if comments only
> > come when patches are posted for merging. None what so ever. So, we've
> > lost the last three weeks because I decided to "be kind" and post RFC.
> > Total waste of effort.
> 
> Sorry, but I don't exactly have a reason to respond to this series earlier
> than others more directly affected, even less so when it's an RFC.
> My feedback is strictly from the point of view of the "other" drivers
> who don't care about context-specific interpretations of the CPU port
> OF node. For them it doesn't make sense to have "default_interface" an
> argument of phylink_get_caps.
> 
> Also about the total waste of effort (or at least time), it's not at all
> obvious to me that if I had provided more feedback earlier, this series
> would have been done with even one day earlier, considering you've stated
> at least twice that you're waiting for a reply from Andrew, which didn't come.

I've given up waiting, basically. I think anyone reasonable will also
have decided the same thing. As I've said, Jakub seems to have given up
waiting for people to review my RFC patches to - this is what Jakub
said to me last week on my RFC series:

| IIUC the folks we expect to pay attention/test have already done so,
| all we can do now is apply and deal with the reports. 5.21 is more
| likely to be LTS than 5.20, right? So no point delaying.

And I really am at the point of agreeing with this - people have had
more than sufficient time to comment, and if they haven't by now, either
they don't care or they're just being difficult and intentionally trying
to stall development effort.

> > Now, on your point... the series posted on the 24th June was using
> > the mv88e6xxx port_max_speed_interface() but discussion off the mailing
> > list:
> > 
> > 20:19 < rmk> kabel: hmm, is mv88e6393x_port_max_speed_mode() correct?
> > 20:20 < rmk> it seems to be suggesting to use PHY_INTERFACE_MODE_10GBASER for
> >              port 9
> > 09:50 < kabel> rmk: yes, 10gbase-r is correct for 6393x. But we need to add
> >                exception for 6191x, as is done in chip.c function
> >                mv88e6393x_phylink_get_caps()
> > 09:51 < kabel> rmk: on 6191x only port 10 supports >1g speeds
> > 11:51 < rmk> kabel: moving it into the get_caps function makes it easier to set
> >              the default_interfaces for 6193x
> > 14:20 < kabel> rmk: yes, get_caps doing it would be better
> > 
> > The problem is this - we call get_caps(), and we have to read registers
> > to work out what the port supports. If we have a separate callback, then
> > we need to re-read those registers to get the same information to report
> > what the default interface should be.
> > 
> > Since almost all of the Marvell implementations the values for both the
> > list of supported interfaces and the default interface both require
> > reading a register and translating it to a phy_interface_t, and then
> > setting the support mask, it seems logical to combine these two
> > functioalities into one function.
> 
> In essence that doesn't mean much; DSA isn't Marvell only, but I'll give
> it to you: if only the Marvell driver (and Broadcom later, I expect) is
> going to add support for the context-specific interpretation of CPU port
> OF nodes, then we may consider tailoring the implementation to their
> hardware register layout details. In any case, my concern can be
> addressed even if you insist on keeping the default interface as an
> argument of phylink_get_caps. There just needs to be a lot more
> documentation explaining who needs to populate that argument and why.

I don't get the point you're making here.

> Also, perhaps more importantly, a real effort needs to be put to prevent
> breakage for drivers that work without a phylink instance registered for
> the CPU port, and also don't report the default interface. Practically
> that just means not deleting the current logic, but making it one of 3
> options.
> 
> fwnode is valid from phylink's perspective?
>        /                             \
>  yes  /                               \ no
>      /                                 \
> register with phylink         can we determine the link parameters to create
>                                   a fixed-link software node?
>                                        /                \                     \
>                                  yes  /                  \  no                |
>                                      /                    \                   | this is missing
>                                     /                      \                  |
>              create the software node and       don't put the port down,      |
>              register with phylink              don't register with phylink   /

This is exactly what we have today, and is exactly what I'm trying to
get rid of, so we have _consistency_ in the implementation, to prevent
fuckups like I've created by converting many DSA drivers to use
phylink_pcs. Any DSA driver that used a PCS for the DSA or CPu port and
has been converted to phylink_pcs support has been broken in the last
few kernel cycles. I'm trying to address that breakage before
converting the Marvell DSA driver - which is the driver that highlighted
the problem.

We need to move away from the current model in DSA where we only use
stuff in random situations.

Well, at this point, I'm just going to give up with this kernel cycle.
It seems impossible to get this sorted. It seems impossible to move
forward with the conversion of Marvell DSA to phylink_pcs. In fact,
I might just give up with the idea of further phylink development
because it's just too fucking difficult, and getting feedback is just
impossible.

-- 
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