From: Oleksij Rempel <o.rempel@pengutronix•de>
To: Andrew Lunn <andrew@lunn•ch>
Cc: "Maxime Chevallier" <maxime.chevallier@bootlin•com>,
"Russell King (Oracle)" <linux@armlinux•org.uk>,
"Kory Maincent" <kory.maincent@bootlin•com>,
davem@davemloft•net, netdev@vger•kernel.org,
linux-kernel@vger•kernel.org, thomas.petazzoni@bootlin•com,
"Jakub Kicinski" <kuba@kernel•org>,
"Eric Dumazet" <edumazet@google•com>,
"Paolo Abeni" <pabeni@redhat•com>,
linux-arm-kernel@lists•infradead.org,
"Christophe Leroy" <christophe.leroy@csgroup•eu>,
"Herve Codina" <herve.codina@bootlin•com>,
"Florian Fainelli" <f.fainelli@gmail•com>,
"Heiner Kallweit" <hkallweit1@gmail•com>,
"Vladimir Oltean" <vladimir.oltean@nxp•com>,
"Marek Behún" <kabel@kernel•org>,
"Nicolò Veronese" <nicveronese@gmail•com>,
"Simon Horman" <horms@kernel•org>,
mwojtas@chromium•org, "Antoine Tenart" <atenart@kernel•org>
Subject: Re: [PATCH net-next RFC 0/5] net: phy: Introduce a port representation
Date: Tue, 7 Jan 2025 17:49:15 +0100 [thread overview]
Message-ID: <Z31bC6ymkKBHdYVR@pengutronix.de> (raw)
In-Reply-To: <Z31ZOjLcE34CNj0S@pengutronix.de>
On Tue, Jan 07, 2025 at 05:41:30PM +0100, Oleksij Rempel wrote:
> On Tue, Jan 07, 2025 at 05:22:51PM +0100, Andrew Lunn wrote:
> > > I have however seen devices that have a 1G PHY connected to a RJ45
> > > port with 2 lanes only, thus limiting the max achievable speed to 100M.
> > > Here, we would explicietly describe the port has having 2 lanes.
>
> I can confirm existence of this kind of designs. One industrial real life
> example: a SoC connected to 3 port Gigabit KSZ switch. One port is
> typical RJ45 connector. Other port is RJ11 connector.
>
> The speed can be reduced by using max-speed property. But i can't
> provide any user usable diagnostic information just by saying pair A or
> B is broken.
>
> This is one of the reasons why i propose detailed description.
Here is one example:
https://www.balluff.com/de-de/products/BNI004F?gad_source=1&gclid=Cj0KCQiAvvO7BhC-ARIsAGFyToUmOy6VpSZUszHQ9X4tuUlyLdtAZqkk3tKxggF5z7D1pk3CgH5IOvwaAhhUEALw_wcB
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next prev parent reply other threads:[~2025-01-07 16:49 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-20 20:14 [PATCH net-next RFC 0/5] net: phy: Introduce a port representation Maxime Chevallier
2024-12-20 20:15 ` [PATCH net-next RFC 1/5] net: ethtool: common: Make BaseT a 4-lanes mode Maxime Chevallier
2024-12-20 20:15 ` [PATCH net-next RFC 2/5] net: ethtool: Introduce ETHTOOL_LINK_MEDIUM_* values Maxime Chevallier
2024-12-20 20:15 ` [PATCH net-next RFC 3/5] net: ethtool: Export the link_mode_params definitions Maxime Chevallier
2024-12-20 20:15 ` [PATCH net-next RFC 4/5] net: phy: Introduce PHY ports representation Maxime Chevallier
2024-12-20 20:15 ` [PATCH net-next RFC 5/5] net: phy: dp83822: Add support for phy_port representation Maxime Chevallier
2024-12-22 15:59 ` [PATCH net-next RFC 0/5] net: phy: Introduce a port representation Oleksij Rempel
2024-12-22 18:54 ` Oleksij Rempel
2025-01-02 10:48 ` Russell King (Oracle)
2025-01-02 17:03 ` Oleksij Rempel
2025-01-07 13:26 ` Kory Maincent
2025-01-07 14:02 ` Oleksij Rempel
2025-01-07 14:43 ` Kory Maincent
2025-01-07 14:53 ` Oleksij Rempel
2025-01-07 15:14 ` Russell King (Oracle)
2025-01-07 15:54 ` Oleksij Rempel
2025-01-07 15:12 ` Russell King (Oracle)
2025-01-07 16:13 ` Andrew Lunn
2025-01-07 16:15 ` Maxime Chevallier
2025-01-07 16:22 ` Andrew Lunn
2025-01-07 16:41 ` Oleksij Rempel
2025-01-07 16:49 ` Oleksij Rempel [this message]
2025-01-08 7:25 ` Maxime Chevallier
2025-01-08 8:12 ` Oleksij Rempel
2025-01-04 22:23 ` Kory Maincent
2025-01-06 18:17 ` Oleksij Rempel
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