Subject: Re: [PATCH net] net: phy: marvell10g: fix 88x3310 power up

From: "Russell King (Oracle)" <[email-masked]>
Date: Thu, 13 Jul 2023 11:46:08 +0100

On Wed, Jul 12, 2023 at 02:26:34PM +0800, Jiawen Wu wrote:
> Clear MV_V2_PORT_CTRL_PWRDOWN bit to set power up for 88x3310 PHY,
> it sometimes does not take effect immediately. This will cause
> mv3310_reset() to time out, which will fail the config initialization.
> So add to poll PHY power up.

Can you check how long it takes for the PWRDOWN bit to clear? The
datasheet says that hardware reset or a MDIO write to this register
can clear this bit. It doesn't say that it needs to be polled or
that it takes time to clear before reset is possible.

So, I think a little more explanation and investigation would be
useful.

Thanks.

-- 
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