Subject: Re: [PATCH net] net: phy: marvell10g: fix 88x3310 power up

From: "Russell King (Oracle)" <[email-masked]>
Date: Mon, 17 Jul 2023 13:22:50 +0100

On Mon, Jul 17, 2023 at 06:51:38PM +0800, Jiawen Wu wrote:
> > > > > There are two places that mv3310_reset() is called, mv3310_config_mdix()
> > > > > and mv3310_set_edpd(). One of them is in the probe function, after we
> > > > > have powered up the PHY.
> > > > >
> > > > > I think we need much more information from the reporter before we can
> > > > > guess which commit is a problem, if any.
> > > > >
> > > > > When does the reset time out?
> > > > > What is the code path that we see mv3310_reset() timing out?
> > > > > Does the problem happen while resuming or probing?
> > > > > How soon after clearing the power down bit is mv3310_reset() called?
> > > >
> > > > I need to test it more times for more information.
> > > >
> > > > As far as I know, reset timeout appears in mv3310_set_edpd(), after mv3310_power_up()
> > > > in mv3310_config_init().
> > > >
> > > > Now what I'm confused about is, sometimes there was weird values while probing, just
> > > > to read out a weird firmware version, that caused the test to fail.
> > > >
> > > > And for this phy_read_mmd_poll_timeout(), it only succeeds when sleep_before_read = true.
> > > > Otherwise, it would never succeed to clear the power down bit. Currently it looks like clearing
> > > > the bit takes about 1ms.
> > >
> > > So, reading the bit before the first delay period results in the bit not
> > > clearing, despite having written it to be zero?
> > 
> > Yes. So in the original code, there is no delay to read the register again for
> > setting software reset bit. I think the power down bit is not actually cleared
> > in my test.
> 
> Hi Russell,
> 
> I confirmed last week that this change is valid to make mv3310_reset() success.
> But now reset fails again, only on port 0. Reset timeout still appears in
> mv3310_config_init() -> mv3310_set_edpd() -> mv3310_reset(). I deleted this
> change to test again, and the result shows that this change is valid for port 1.
> 
> So I'm a little confused. Since I don't have programming guidelines for this PHY,
> but only a datasheet. Could you please help to check for any possible problems
> with it?

I think the question that's missing is... why do other 88x3310 users not
see this problem - what is special about your port 0?

Maybe there's a clue with the hardware schematics? Do you have access to
those?

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