Subject: Re: [PATCH net] net: phy: marvell10g: fix 88x3310 power up

From: "Russell King (Oracle)" <[email-masked]>
Date: Wed, 19 Jul 2023 09:52:01 +0100

On Wed, Jul 19, 2023 at 04:38:36PM +0800, Jiawen Wu wrote:
> On Wednesday, July 19, 2023 4:27 PM, Russell King (Oracle) wrote:
> > On Wed, Jul 19, 2023 at 03:57:30PM +0800, Jiawen Wu wrote:
> > > > According to this read though (which is in get_mactype), the write
> > > > didn't take effect.
> > > >
> > > > If you place a delay of 1ms after phy_clear_bits_mmd() in
> > > > mv3310_power_up(), does it then work?
> > >
> > > Yes, I just experimented, it works well.
> > 
> > Please send a patch adding it, with a comment along the lines of:
> > 
> > 	/* Sometimes, the power down bit doesn't clear immediately, and
> > 	 * a read of this register causes the bit not to clear. Delay
> > 	 * 1ms to allow the PHY to come out of power down mode before
> > 	 * the next access.
> > 	 */
> 
> After multiple experiments, I determined that the minimum delay it required
> is 55us. Does the delay need to be reduced? But I'm not sure whether it is
> related to the system. I use udelay(55) in the test.

55us is slightly longer than one access-time to C45 registers with 32
bits of preamble on the bus before each mdio frame. I'd suggest we go
with 100us in that case.

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