Subject: Re: [PATCH 0/2] net: stmmac: allow sharing MDIO lines

From: "Russell King (Oracle)" <[email-masked]>
Date: Tue, 8 Aug 2023 14:26:29 +0100

On Tue, Aug 08, 2023 at 10:13:09AM +0200, Bartosz Golaszewski wrote:
> Ok so upon some further investigation, the actual culprit is in stmmac
> platform code - it always tries to register an MDIO bus - independent
> of whether there is an actual mdio child node - unless the MAC is
> marked explicitly as having a fixed-link.
> 
> When I fixed that, MAC1's probe is correctly deferred until MAC0 has
> created the MDIO bus.
> 
> Even so, isn't it useful to actually reference the shared MDIO bus in some way?
> 
> If the schematics look something like this:
> 
> --------           -------
> | MAC0 |--MDIO-----| PHY |
> -------- |     |   -------
>          |     |
> -------- |     |   -------
> | MAC1 |--     ----| PHY |
> --------           -------
> 
> Then it would make sense to model it on the device tree?

So I think what you're saying is that MAC0 and MAC1's have MDIO bus
masters, and the hardware designer decided to tie both together to
a single set of clock and data lines, which then go to two PHYs.

In that case, I would strongly advise only registering one MDIO bus,
and avoid registering the second one - thereby preventing any issues
caused by both MDIO bus masters trying to talk at the same time.

The PHYs should be populated in firmware on just one of the buses.

You will also need to ensure that whatever registers the bus does
make sure that the clocks necessary for communicating on the bus
are under control of the MDIO bus code and not the ethernet MAC
code. We've run into problems in the past where this has not been
the case, and it means - taking your example above - that when MAC1
wants to talk to its PHY, if MAC0 isn't alive it can't.

So just be aware of the clocking situation and make sure that your
MDIO bus code is managing the clocks necessary for the MDIO bus
master to work.

In regard to sharing of the MDIO bus signals between two bus
masters, I do not believe that is permissible - there's no
collision detection in hardware like there is on I²C. So
having two MDIO bus masters talking at the same time would
end up corrupting the MDC (clock) and MDIO (data) signals if
both were active at the same time.

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