Subject: Re: [PATCH] net: phy: at803x: Improve hibernation support on start up

From: "Russell King (Oracle)" <[email-masked]>
Date: Thu, 10 Aug 2023 11:01:53 +0100

On Thu, Aug 10, 2023 at 02:49:55AM +0200, Marek Vasut wrote:
> On 8/10/23 00:06, Andrew Lunn wrote:
> > On Wed, Aug 09, 2023 at 11:34:19PM +0200, Marek Vasut wrote:
> > > On 8/9/23 15:40, Andrew Lunn wrote:
> > > > > > Hm.. how about officially defining this PHY as the clock provider and disable
> > > > > > PHY automatic hibernation as long as clock is acquired?
> > > > > > 
> > > > > Sorry, I don't know much about the clock provider/consumer, but I think there
> > > > > will be more changes if we use clock provider/consume mechanism.
> > > > 
> > > > Less changes is not always best. What happens when a different PHY is
> > > > used?
> > > 
> > > Then the system wouldn't be affected by this AR803x specific behavior.
> > 
> > Do you know it really is specific to the AR803x? Turning the clock off
> > seams a reasonable thing to do when saving power, or when there is no
> > link partner.
> 
> This hibernation behavior seem specific to this PHY, I haven't seen it on
> another PHY connected to the EQoS so far.

Marvell PHYs can be programmed so that RXCLK stops when the PHY
enters power down or energy-detect state, although it defaults to
always keeping the RGMII interface powered (and thus providing a
clock.)

One Micrel PHY - "To save more power, the KSZ9031RNX stops the RX_CLK
clock output to the MAC after 10 or more RX_CLK clock
cycles have occurred in the receive LPI state." which seems to imply
if EEE is enabled, then the receive clock will be stopped when
entering low-power state.

I've said this several times in this thread - I think we need a bit
in the PHY device's dev_flags to allow the MAC to say "do not power
down the receive clock" which is used by the PHY drivers to (a) program
the hardware to prevent the receive clock being stopped in situations
such as the AR803x hibernate mode, and (b) to program the hardware not
to stop the receive clock when entering EEE low power. This does seem
to be a generic thing and not specific to just one PHY - especially as
the stopping of clocks when entering EEE low power is a IEEE 802.3
defined thing.

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