Subject: Synopsys XGMII MAC and USXGMII interfaces

From: "Russell King (Oracle)" <[email-masked]>
Date: Wed, 23 Aug 2023 11:58:32 +0100

Part 2 of the discussion...

A similar issue applies to PHY_INTERFACE_MODE_USXGMII, but is reversed.
USXGMII supports 10M, 100M, 1G, 2.5G, 5G and 10G. Phylink allows all of
these because that's what the appropriate standard says. dwxgmac2
initialises config register settings for speeds from 10M up to 10G.
However, the PHY_INTERFACE_MODE_USXGMII switch() block in
stmmac_mac_link_up() only handles 2.5G, 5G and 10G. Shouldn't it handle
the other speed cases - it looks like the MAC does support them.

The initialisation done by dwxgmac2_setup() does setup control register
masks for everything from 10M to 10G, so on the face of it, it looks
like a mistake in stmmac_mac_link_up().

If it's something outside of the MAC that doesn't support these speeds
when operating as USXGMII, then that needs to be handled.

The other weird thing is that when using PHY_INTERFACE_MODE_USXGMII
with XPCS, XPCS supports 1G, 2.5G and 10G ethtool link modes, but not
5G. So combining the implementation in stmmac_mac_link_up(), that
means only 2.5G and 10G can actually be functional. Is that a fair
assessment of the USXGMII situation with stmmac?

Thanks.

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