Subject: Re: [PATCH net] net: stmmac: update Rx clk divider for 10M SGMII

From: "Russell King (Oracle)" <[email-masked]>
Date: Fri, 24 Nov 2023 09:12:04 +0000

On Fri, Nov 24, 2023 at 10:38:18AM +0530, Sneh Shah wrote:
>  #define RGMII_CONFIG_LOOPBACK_EN		BIT(2)
>  #define RGMII_CONFIG_PROG_SWAP			BIT(1)
>  #define RGMII_CONFIG_DDR_MODE			BIT(0)
> +#define RGMII_CONFIG_SGMII_CLK_DVDR		GENMASK(18, 10)

So you're saying here that this is a 9 bit field...

> @@ -617,6 +618,8 @@ static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)
>  	case SPEED_10:
>  		val |= ETHQOS_MAC_CTRL_PORT_SEL;
>  		val &= ~ETHQOS_MAC_CTRL_SPEED_MODE;
> +		rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR, BIT(10) |
> +			      GENMASK(15, 14), RGMII_IO_MACRO_CONFIG);

... and then you use GENMASK(15,14) | BIT(10) here to set bits in that
bitfield. If there are multiple bitfields, then these should be defined
separately and the mask built up.

I suspect that they aren't, and you're using this to generate a _value_
that has bits 5, 4, and 0 set for something that really takes a _value_.
So, FIELD_PREP(RGMII_CONFIG_SGMII_CLK_DVDR, 0x31) or
FIELD_PREP(RGMII_CONFIG_SGMII_CLK_DVDR, 49) would be entirely correct
here.

The next concern I have is that you're only doing this for SPEED_10.
If it needs to be programmed for SPEED_10 to work, and not any of the
other speeds, isn't this something that can be done at initialisation
time? If it has to be done depending on the speed, then don't you need
to do this for each speed with an appropriate value?

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