Subject: Re: [PATCH net] net: stmmac: update Rx clk divider for 10M SGMII

From: "Russell King (Oracle)" <[email-masked]>
Date: Mon, 27 Nov 2023 10:05:18 +0000

On Mon, Nov 27, 2023 at 03:17:20PM +0530, Sneh Shah wrote:
> On 11/27/2023 2:09 PM, Russell King (Oracle) wrote:
> > On Mon, Nov 27, 2023 at 11:25:34AM +0530, Sneh Shah wrote:
> >> On 11/24/2023 2:42 PM, Russell King (Oracle) wrote:
> >>> The next concern I have is that you're only doing this for SPEED_10.
> >>> If it needs to be programmed for SPEED_10 to work, and not any of the
> >>> other speeds, isn't this something that can be done at initialisation
> >>> time? If it has to be done depending on the speed, then don't you need
> >>> to do this for each speed with an appropriate value?
> >>
> >> This field programming is required only for 10M speed in for SGMII mode. other speeds are agnostic to this field. Hence we are programming it always when SGMII link comes up in 10M mode. init driver data for ethqos is common for sgmii and rgmii. As this fix is specific to SGMII we can't add this to init driver data.
> > 
> > I wasn't referring to adding it to driver data. I was asking whether it
> > could be done in the initialisation path.
> > 
> No, IOMACRO block is configured post phylink up regardless of RGMII or SGMII mode. We are not updating them at driver initialization time itself.

What reason (in terms of the hardware) requires you to do this every
time you select 10M speed? Does the hardware change the value in the
register?

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