Subject: Re: [net-next PATCH v2] net: phy: aquantia: drop wrong endianness conversion for addr and CRC

From: "Russell King (Oracle)" <[email-masked]>
Date: Tue, 28 Nov 2023 13:06:56 +0000

On Tue, Nov 28, 2023 at 01:44:39PM +0100, Christian Marangi wrote:
> Also the CRC returned from the mailbox CRC has to be converted with
> le16_to_cpu since it's LE and won't match on BE system. Am I wrong?

I think you are. As I've said before, everything transferred over the
MDIO bus is totally independent of the CPU endianness. Bit 0 in the
registers on the PHY will appear in bit 0 of the CPU register, and
bit 15 in the registers on the PHY will appear in bit 15 of the CPU
register.

If this weren't the case, then if we access the BMCR register, and
the BMCR contains 0x1140 (indicating AN is enabled, full duplex,
1000Mbps) then if these were CPU endian-dependent, we'd end up reading
0x4011, and that will break phylib _and_ user applications (these
register definitions are exported to userspace.)

-- 
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