Subject: Re: [PATCH net-next v8 2/2] net: stmmac: Add support for Allwinner A523 GMAC200

From: "Russell King (Oracle)" <[email-masked]>
Date: Wed, 1 Oct 2025 08:48:39 +0100

On Wed, Oct 01, 2025 at 09:25:07AM +0200, Paolo Abeni wrote:
> On 10/1/25 2:20 AM, Jakub Kicinski wrote:
> > On Mon, 29 Sep 2025 18:08:04 -0700 Jakub Kicinski wrote:
> >> On Fri, 26 Sep 2025 03:15:59 +0800 Chen-Yu Tsai wrote:
> >>> The Allwinner A523 SoC family has a second Ethernet controller, called
> >>> the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for
> >>> numbering. This controller, according to BSP sources, is fully
> >>> compatible with a slightly newer version of the Synopsys DWMAC core.
> >>> The glue layer around the controller is the same as found around older
> >>> DWMAC cores on Allwinner SoCs. The only slight difference is that since
> >>> this is the second controller on the SoC, the register for the clock
> >>> delay controls is at a different offset. Last, the integration includes
> >>> a dedicated clock gate for the memory bus and the whole thing is put in
> >>> a separately controllable power domain.  
> >>
> >> Hi Andrew, does this look good ?
> >>
> >> thread: https://lore.kernel.org/[email-masked]
> > 
> > Adding Heiner and Russell, in case Andrew is AFK.
> > 
> > We need an ack from PHY maintainers, the patch seems to be setting
> > delays regardless of the exact RMII mode. I don't know these things..
> 
> The net-next PR is upon us, let's defer even this series to the next cycle.

Would've been nice to have been given the opportunity to respond to
Jakub's email before that decision was made. Not all of us are in
the US timezone. (Jakub's email came in gone 1am my time.)

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