Subject: Re: [PATCH net-next v8 2/2] net: stmmac: Add support for Allwinner A523 GMAC200

From: "Russell King (Oracle)" <[email-masked]>
Date: Wed, 1 Oct 2025 08:47:06 +0100

On Tue, Sep 30, 2025 at 05:20:22PM -0700, Jakub Kicinski wrote:
> On Mon, 29 Sep 2025 18:08:04 -0700 Jakub Kicinski wrote:
> > On Fri, 26 Sep 2025 03:15:59 +0800 Chen-Yu Tsai wrote:
> > > The Allwinner A523 SoC family has a second Ethernet controller, called
> > > the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for
> > > numbering. This controller, according to BSP sources, is fully
> > > compatible with a slightly newer version of the Synopsys DWMAC core.
> > > The glue layer around the controller is the same as found around older
> > > DWMAC cores on Allwinner SoCs. The only slight difference is that since
> > > this is the second controller on the SoC, the register for the clock
> > > delay controls is at a different offset. Last, the integration includes
> > > a dedicated clock gate for the memory bus and the whole thing is put in
> > > a separately controllable power domain.  
> > 
> > Hi Andrew, does this look good ?
> > 
> > thread: https://lore.kernel.org/[email-masked]
> 
> Adding Heiner and Russell, in case Andrew is AFK.

I believe it's fine. Applying the delays irrespective of the RGMII mode
is what I think needs to be done to allow the delays to be fine-tuned.

The author hsa confirmed that the delays don't apply to RMII, so that
isn't a concern. So,

Reviewed-by: Russell King (Oracle) <[email-masked]>

Thanks!

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