Subject: Re: [PATCH net-next v2 2/3] net: stmmac: Add glue driver for Motorcomm YT6801 ethernet controller

From: Yao Zi <[email-masked]>
Date: Sat, 15 Nov 2025 11:46:36 +0000

On Tue, Nov 11, 2025 at 12:32:56PM +0000, Russell King (Oracle) wrote:
> On Tue, Nov 11, 2025 at 10:52:51AM +0000, Yao Zi wrote:
> > +	plat->bus_id		= pci_dev_id(pdev);
> > +	plat->phy_addr		= -1;
> > +	plat->phy_interface	= PHY_INTERFACE_MODE_GMII;
> > +	plat->clk_csr		= STMMAC_CSR_20_35M;
> 
> Could you include a comment indicating what the stmmac clock rate
> actually is (the rate which is used to derive this divider) ? As
> this is PCI, I'm guessing it's 33MHz, which fits with your divider
> value.

The divider is taken from vendor driver, and the clock path isn't
mentioned in the datasheet, either. I don't think it's 33MHz since it's
a PCIe chip, and there's no 33MHz clock supplied by PCIe.

The datasheet[1] (Chinese website, requires login) mentions that the
controller requires a 25MHz external clock input/oscillator to function,

> 25MHz Crystal Input pin.
>
> If use external oscillator or clock from another device.
>   1. When connect an external 25MHz oscillator or clock from another
>   device to XTAL_O pin, XTAL_I must be shorted to GND.
>   2. When connect an external 25MHz oscillator or clock from another
>   device to XTAL_I pin, keep the XTAL_O floating.

25MHz fits in STMMAC_CSR_20_35M, too, so it's more likely the clock
source.

I don't think this guess could be confirmed without vendor's help,
should the information be included as comment?

Best regards,
Yao Zi

[1]: https://www.motor-comm.com/download?kw=&category=606&wd=1&tp=1

> Thanks.
> 
> -- 
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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