Subject: Re: [RFC PATCH net-next v4 1/3] net: phy: motorcomm: Support YT8531S PHY in YT6801 Ethernet controller

From: Yao Zi <[email-masked]>
Date: Tue, 23 Dec 2025 17:40:10 +0000

On Sun, Dec 21, 2025 at 09:29:01PM +0100, Andrew Lunn wrote:
> On Tue, Dec 16, 2025 at 06:03:29PM +0000, Yao Zi wrote:
> > YT6801's internal PHY is confirmed as a GMII-capable variant of YT8531S
> > by a previous series[1] and reading PHY ID. Add support for
> > PHY_INTERFACE_MODE_GMII for YT8531S to allow the Ethernet driver to
> > reuse the PHY code for its internal PHY.
> > 
> > Link: https://lore.kernel.org/all/[email-masked]/ # [1]
> > Co-developed-by: Frank Sae <[email-masked]>
> > Signed-off-by: Frank Sae <[email-masked]>
> > Signed-off-by: Yao Zi <[email-masked]>
> > ---
> >  drivers/net/phy/motorcomm.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
> > index 89b5b19a9bd2..b751fbc6711a 100644
> > --- a/drivers/net/phy/motorcomm.c
> > +++ b/drivers/net/phy/motorcomm.c
> > @@ -910,6 +910,10 @@ static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev)
> >  		val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg) |
> >  		       FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg);
> >  		break;
> > +	case PHY_INTERFACE_MODE_GMII:
> > +		if (phydev->drv->phy_id != PHY_ID_YT8531S)
> > +			return -EOPNOTSUPP;
> > +		break;
> 
> You have a break here. So the write to RGMII delay register will be
> performed, even thought this is an GMII PHY. Does the register exists?

With testing it seems the register simply makes no effect on the YT8531S
PHY integrated in YT6801.

> Would it be better to just return 0;

However, returning early here could avoid possible confusion. Will
change it in v5.

>       Andrew

Regards,
Yao Zi