Subject: Re: [RFC PATCH] net: phy: integrate reset-after-clock quirk into phy_init_hw

From: "Russell King (Oracle)" <[email-masked]>
Date: Wed, 28 Jan 2026 22:48:01 +0000

On Wed, Jan 28, 2026 at 10:17:41PM +0000, Russell King (Oracle) wrote:
> As I've just mentioned earlier in this thread, there seems to be nothing
> special about the LAN8710-like PHYs requiring their XTAL clock to be
> running for reset to be functional. The same is true of AR8035 used
> on i.MX6 SolidRun platforms, and Marvell 88E151x PHYs that I've looked
> at. I would suggest that, in general, _all_ PHYs require their XTAL
> clock to be running.
> 
> Therefore, this is not a work of the PHY at all.
> 
> It is a quirk of the board design to provide the PHY's XTAL clock from
> the SoC, and this _seems_ to be common with FEC based systems, probably
> because there's an easy way to get the clock from the FEC, thus saving
> the cost of a crystal.
> 
> I stated how SolidRun handles this quirk entirely in uboot so the kernel
> doesn't have to care about this at all, and the kernel doesn't get to
> even know that the PHY has a reset GPIO.

I've just been looking at the ZII dev rev B board, which uses a VF610
with a KSZ8041 PHY. It sources its clock from the SoC as well. However,
looking at the PHY datasheet, no clock is specified required during
reset.

However, from what I can see, similar to the SolidRun platforms, the
clock for the PHY isn't described in DT. It goes further though - nor
is the PHY described, nor is the PHYs reset signal (which comes from
io-expander@20).

-- 
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