From: Jiri Pirko <jiri@resnulli•us>
To: Grzegorz Nitka <grzegorz.nitka@intel•com>
Cc: netdev@vger•kernel.org, linux-kernel@vger•kernel.org,
intel-wired-lan@lists•osuosl.org, poros@redhat•com,
richardcochran@gmail•com, andrew+netdev@lunn•ch,
przemyslaw.kitszel@intel•com, anthony.l.nguyen@intel•com,
Prathosh.Satish@microchip•com, ivecera@redhat•com,
arkadiusz.kubalewski@intel•com, vadim.fedorenko@linux•dev,
donald.hunter@gmail•com, horms@kernel•org, pabeni@redhat•com,
kuba@kernel•org, davem@davemloft•net, edumazet@google•com,
Aleksandr Loktionov <aleksandr.loktionov@intel•com>
Subject: Re: [PATCH v11 net-next 4/8] dpll: allow fwnode pins to attempt state change without capability bit
Date: Tue, 26 May 2026 15:27:49 +0200 [thread overview]
Message-ID: <ahWf0HAr3sRfXw0Q@FV6GYCPJ69> (raw)
In-Reply-To: <20260526093419.639220-5-grzegorz.nitka@intel.com>
Tue, May 26, 2026 at 11:34:15AM +0200, grzegorz.nitka@intel•com wrote:
>Pins registered with an fwnode may have .state_on_dpll_set implemented
>without advertising DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE upfront.
>Requiring the bit for fwnode pins ties firmware description to driver
>implementation details unnecessarily.
>
>Relax the capability check in dpll_pin_state_set() and
>dpll_pin_on_pin_state_set(): when a pin has an associated fwnode, bypass
>the capability gate and let the ops layer decide, returning -EOPNOTSUPP
>if .state_on_dpll_set is absent. Non-fwnode pins retain the original
>strict behavior.
>
>This is used later in the series by the SyncE_Ref output pin, which
>relies on the fwnode path for state control.
>
>Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel•com>
>Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel•com>
Reviewed-by: Jiri Pirko <jiri@nvidia•com>
next prev parent reply other threads:[~2026-05-26 13:27 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-26 9:34 [PATCH v11 net-next 0/8] dpll/ice: Add generic DPLL type and full TX reference clock control for E825 Grzegorz Nitka
2026-05-26 9:34 ` [PATCH v11 net-next 1/8] dpll: add generic DPLL type Grzegorz Nitka
2026-05-26 13:28 ` Jiri Pirko
2026-05-26 9:34 ` [PATCH v11 net-next 2/8] dpll: allow registering FW-identified pin with a different DPLL Grzegorz Nitka
2026-05-26 9:34 ` [PATCH v11 net-next 3/8] dpll: extend pin notifier with notification source ID Grzegorz Nitka
2026-05-26 13:27 ` Jiri Pirko
2026-05-26 9:34 ` [PATCH v11 net-next 4/8] dpll: allow fwnode pins to attempt state change without capability bit Grzegorz Nitka
2026-05-26 13:27 ` Jiri Pirko [this message]
2026-05-26 9:34 ` [PATCH v11 net-next 5/8] ice: introduce TXC DPLL device and TX ref clock pin framework for E825 Grzegorz Nitka
2026-05-28 8:55 ` [Intel-wired-lan] " Loktionov, Aleksandr
2026-05-26 9:34 ` [PATCH v11 net-next 6/8] ice: implement CPI support for E825C Grzegorz Nitka
2026-05-28 8:55 ` [Intel-wired-lan] " Loktionov, Aleksandr
2026-05-28 12:24 ` Loktionov, Aleksandr
2026-05-29 14:35 ` Nitka, Grzegorz
2026-05-26 9:34 ` [PATCH v11 net-next 7/8] ice: add Tx reference clock index handling to AN restart command Grzegorz Nitka
2026-05-26 9:34 ` [PATCH v11 net-next 8/8] ice: implement E825 TX ref clock control and TXC hardware sync status Grzegorz Nitka
2026-05-28 12:21 ` [Intel-wired-lan] " Loktionov, Aleksandr
2026-05-29 15:08 ` Nitka, Grzegorz
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