Subject: Re: Info: NAPI performance at "low" loads

From: [email-masked] (Eric W. Biederman)
Date: 18 Sep 2002 11:27:34 -0600

"David S. Miller" <[email-masked]> writes:

>    From: jamal <[email-masked]>
>    Date: Tue, 17 Sep 2002 20:57:58 -0400 (EDT)
>    
>    I am not so sure with that 6% difference there is no other bug lurking
>    there; 6% seems too large for an extra two PCI transactions per packet.
> 
> {in,out}{b,w,l}() operations have a fixed timing, therefore his
> results doesn't sound that far off.
????

I don't see why they should be.  If it is a pci device the cost should
the same as a pci memory I/O.  The bus packets are the same.  So things like
increasing the pci bus speed should make it take less time.

Plus I have played with calibrating the TSC with outb to port
0x80 and there was enough variation that it was unuseable.  On some
newer systems it would take twice as long as on some older ones.

Eric