From: <Nicolas.Ferre@microchip•com>
To: <Eugen.Hristev@microchip•com>, <mturquette@baylibre•com>,
<sboyd@kernel•org>, <alexandre.belloni@bootlin•com>,
<linux-clk@vger•kernel.org>,
<linux-arm-kernel@lists•infradead.org>,
<linux-kernel@vger•kernel.org>
Subject: Re: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL
Date: Wed, 11 Sep 2019 07:03:08 +0000 [thread overview]
Message-ID: <0e8083a3-9443-e2f0-d4a3-1b02a5728759@microchip.com> (raw)
In-Reply-To: <1568183622-7858-1-git-send-email-eugen.hristev@microchip.com>
On 11/09/2019 at 08:39, Eugen Hristev - M18282 wrote:
> From: Eugen Hristev <eugen.hristev@microchip•com>
>
> The PLL input range needs to be able to allow 24 Mhz crystal as input
> Update the range accordingly in plla characteristics struct
>
> Signed-off-by: Eugen Hristev <eugen.hristev@microchip•com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip•com>
Thanks Eugen!
Best regards,
Nicolas
> ---
> drivers/clk/at91/sama5d2.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
> index 6509d09..0de1108 100644
> --- a/drivers/clk/at91/sama5d2.c
> +++ b/drivers/clk/at91/sama5d2.c
> @@ -21,7 +21,7 @@ static const struct clk_range plla_outputs[] = {
> };
>
> static const struct clk_pll_characteristics plla_characteristics = {
> - .input = { .min = 12000000, .max = 12000000 },
> + .input = { .min = 12000000, .max = 24000000 },
> .num_output = ARRAY_SIZE(plla_outputs),
> .output = plla_outputs,
> .icpll = plla_icpll,
>
--
Nicolas Ferre
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next prev parent reply other threads:[~2019-09-11 7:05 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-11 6:39 [PATCH] clk: at91: allow 24 Mhz clock as input for PLL Eugen.Hristev
2019-09-11 7:03 ` Nicolas.Ferre [this message]
2019-09-12 11:06 ` Alexander Dahl
2019-09-12 11:28 ` Eugen.Hristev
2019-09-16 19:52 ` Stephen Boyd
2019-09-17 5:59 ` Eugen.Hristev
2019-09-18 5:00 ` Stephen Boyd
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