Re: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL

From: <Eugen.Hristev@microchip•com>
To: <ada@thorsis•com>, <linux-arm-kernel@lists•infradead.org>
Cc: sboyd@kernel•org, linux-kernel@vger•kernel.org,
	mturquette@baylibre•com, alexandre.belloni@bootlin•com,
	linux-clk@vger•kernel.org
Subject: Re: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL
Date: Thu, 12 Sep 2019 11:28:00 +0000	[thread overview]
Message-ID: <a208cec2-7aa6-e6e8-e6e0-f37769273d5d@microchip.com> (raw)
In-Reply-To: <30755021.BkS3ObC0RA@ada>

On 12.09.2019 14:06, Alexander Dahl wrote:

> 
> Hello,
> 
> out of curiosity: The SAMA5D27-SOM1-EK board has a 24 MHz crystal, that is
> also what /sys/kernel/debug/clk/clk_summary says and the board runs without
> obvious problems. What is this change improving in real practice then?
> 

The board works, but, the characteristics of the PLL are incorrect.
This can lead to unwanted behavior, like calculating wrong minimum 
values for multipliers, or other issues

In this code here in clk-pll.c for example

if (parent_rate > characteristics->input.max) {
                 tmpdiv = DIV_ROUND_UP(parent_rate, 
characteristics->input.max);
                 if (tmpdiv > PLL_DIV_MAX) 

                         return -ERANGE; 

                 if (tmpdiv > mindiv) 

                         mindiv = tmpdiv; 

         }

The divisor is capped by checks, but at another possible requested 
parent rate, this may lead to something wrong, like here, the minimum 
divisor might be greater than what is the real possible one. So in some 
cases it can happen that unwanted results occur.

We may consider at some points to rely on these values more, so, it's 
obvious that they should be correct in the characteristics

So short answer: no improve in your case , where the rates required are 
around 492 Mhz cpu/132 mhz bus (IIRC), but the characteristics need to 
be correct to cover all possible cases.

Eugen

> Greets
> Alex
> 
> Am Mittwoch, 11. September 2019, 06:39:20 CEST schrieb
> Eugen.Hristev@microchip•com:
>> From: Eugen Hristev <eugen.hristev@microchip•com>
>>
>> The PLL input range needs to be able to allow 24 Mhz crystal as input
>> Update the range accordingly in plla characteristics struct
>>
>> Signed-off-by: Eugen Hristev <eugen.hristev@microchip•com>
>> ---
>>   drivers/clk/at91/sama5d2.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
>> index 6509d09..0de1108 100644
>> --- a/drivers/clk/at91/sama5d2.c
>> +++ b/drivers/clk/at91/sama5d2.c
>> @@ -21,7 +21,7 @@ static const struct clk_range plla_outputs[] = {
>>   };
>>
>>   static const struct clk_pll_characteristics plla_characteristics = {
>> -	.input = { .min = 12000000, .max = 12000000 },
>> +	.input = { .min = 12000000, .max = 24000000 },
>>   	.num_output = ARRAY_SIZE(plla_outputs),
>>   	.output = plla_outputs,
>>   	.icpll = plla_icpll,
> 
> 
> 
> 
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