* [PATCH 1/4] Revert "ARM: shmobile: emev2: Replace modify_scu_cpu_psr with scu_power_mode"
2012-11-13 3:10 [GIT PULL] Renesas ARM-based SoC for v3.8 #4 Simon Horman
@ 2012-11-13 3:10 ` Simon Horman
2012-11-13 3:10 ` [PATCH 2/4] Revert "ARM: shmobile: sh73a0: " Simon Horman
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Simon Horman @ 2012-11-13 3:10 UTC (permalink / raw)
To: linux-arm-kernel
This reverts commit 865d90f80384d62e6fbe835159cb674dec32ccb5.
The code changes the flags of the wrong cpus - which breaks the whole
bootup of secondary CPUs.
Cc: Bastian Hecht <hechtb@gmail•com>
Signed-off-by: Simon Horman <horms@verge•net.au>
---
arch/arm/mach-shmobile/smp-emev2.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 535426c..f674562 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -32,8 +32,24 @@
#define EMEV2_SCU_BASE 0x1e000000
+static DEFINE_SPINLOCK(scu_lock);
static void __iomem *scu_base;
+static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
+{
+ unsigned long tmp;
+
+ /* we assume this code is running on a different cpu
+ * than the one that is changing coherency setting */
+ spin_lock(&scu_lock);
+ tmp = readl(scu_base + 8);
+ tmp &= ~clr;
+ tmp |= set;
+ writel(tmp, scu_base + 8);
+ spin_unlock(&scu_lock);
+
+}
+
static unsigned int __init emev2_get_core_count(void)
{
if (!scu_base) {
@@ -79,7 +95,7 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *
cpu = cpu_logical_map(cpu);
/* enable cache coherency */
- scu_power_mode(scu_base, 0);
+ modify_scu_cpu_psr(0, 3 << (cpu * 8));
/* Tell ROM loader about our vector (in headsmp.S) */
emev2_set_boot_vector(__pa(shmobile_secondary_vector));
@@ -90,10 +106,12 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *
static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
{
+ int cpu = cpu_logical_map(0);
+
scu_enable(scu_base);
/* enable cache coherency on CPU0 */
- scu_power_mode(scu_base, 0);
+ modify_scu_cpu_psr(0, 3 << (cpu * 8));
}
static void __init emev2_smp_init_cpus(void)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/4] Revert "ARM: shmobile: sh73a0: Replace modify_scu_cpu_psr with scu_power_mode"
2012-11-13 3:10 [GIT PULL] Renesas ARM-based SoC for v3.8 #4 Simon Horman
2012-11-13 3:10 ` [PATCH 1/4] Revert "ARM: shmobile: emev2: Replace modify_scu_cpu_psr with scu_power_mode" Simon Horman
@ 2012-11-13 3:10 ` Simon Horman
2012-11-13 3:10 ` [PATCH 3/4] Revert "ARM: shmobile: r8a7779: " Simon Horman
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Simon Horman @ 2012-11-13 3:10 UTC (permalink / raw)
To: linux-arm-kernel
This reverts commit e721295185535ed6ef4711eba156fbf5c24f9c5e.
The code changes the flags of the wrong cpus - which breaks the whole
bootup of secondary CPUs.
Cc: Bastian Hecht <hechtb@gmail•com>
Signed-off-by: Simon Horman <horms@verge•net.au>
---
arch/arm/mach-shmobile/smp-sh73a0.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 96ddb97..624f00f 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -41,6 +41,9 @@ static void __iomem *scu_base_addr(void)
return (void __iomem *)0xf0000000;
}
+static DEFINE_SPINLOCK(scu_lock);
+static unsigned long tmp;
+
#ifdef CONFIG_HAVE_ARM_TWD
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
void __init sh73a0_register_twd(void)
@@ -49,6 +52,20 @@ void __init sh73a0_register_twd(void)
}
#endif
+static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
+{
+ void __iomem *scu_base = scu_base_addr();
+
+ spin_lock(&scu_lock);
+ tmp = __raw_readl(scu_base + 8);
+ tmp &= ~clr;
+ tmp |= set;
+ spin_unlock(&scu_lock);
+
+ /* disable cache coherency after releasing the lock */
+ __raw_writel(tmp, scu_base + 8);
+}
+
static unsigned int __init sh73a0_get_core_count(void)
{
void __iomem *scu_base = scu_base_addr();
@@ -66,7 +83,7 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
cpu = cpu_logical_map(cpu);
/* enable cache coherency */
- scu_power_mode(scu_base_addr(), 0);
+ modify_scu_cpu_psr(0, 3 << (cpu * 8));
if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3)
__raw_writel(1 << cpu, WUPCR); /* wake up */
@@ -78,6 +95,8 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
{
+ int cpu = cpu_logical_map(0);
+
scu_enable(scu_base_addr());
/* Map the reset vector (in headsmp.S) */
@@ -85,7 +104,7 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
__raw_writel(__pa(shmobile_secondary_vector), SBAR);
/* enable cache coherency on CPU0 */
- scu_power_mode(scu_base_addr(), 0);
+ modify_scu_cpu_psr(0, 3 << (cpu * 8));
}
static void __init sh73a0_smp_init_cpus(void)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/4] Revert "ARM: shmobile: r8a7779: Replace modify_scu_cpu_psr with scu_power_mode"
2012-11-13 3:10 [GIT PULL] Renesas ARM-based SoC for v3.8 #4 Simon Horman
2012-11-13 3:10 ` [PATCH 1/4] Revert "ARM: shmobile: emev2: Replace modify_scu_cpu_psr with scu_power_mode" Simon Horman
2012-11-13 3:10 ` [PATCH 2/4] Revert "ARM: shmobile: sh73a0: " Simon Horman
@ 2012-11-13 3:10 ` Simon Horman
2012-11-13 3:10 ` [PATCH 4/4] sh: clkfwk: fixup unsed variable warning Simon Horman
2012-11-13 12:50 ` [GIT PULL] Renesas ARM-based SoC for v3.8 #4 Arnd Bergmann
4 siblings, 0 replies; 6+ messages in thread
From: Simon Horman @ 2012-11-13 3:10 UTC (permalink / raw)
To: linux-arm-kernel
This reverts commit cdc7594e5c5f7509a86b205edeedc58d72dd3999.
The code changes the flags of the wrong cpus - which breaks the whole
bootup of secondary CPUs.
Cc: Bastian Hecht <hechtb@gmail•com>
Signed-off-by: Simon Horman <horms@verge•net.au>
---
arch/arm/mach-shmobile/smp-r8a7779.c | 25 ++++++++++++++++++++++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 9def0f2..2ce6af9 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -61,6 +61,9 @@ static void __iomem *scu_base_addr(void)
return (void __iomem *)0xf0000000;
}
+static DEFINE_SPINLOCK(scu_lock);
+static unsigned long tmp;
+
#ifdef CONFIG_HAVE_ARM_TWD
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
@@ -70,6 +73,20 @@ void __init r8a7779_register_twd(void)
}
#endif
+static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
+{
+ void __iomem *scu_base = scu_base_addr();
+
+ spin_lock(&scu_lock);
+ tmp = __raw_readl(scu_base + 8);
+ tmp &= ~clr;
+ tmp |= set;
+ spin_unlock(&scu_lock);
+
+ /* disable cache coherency after releasing the lock */
+ __raw_writel(tmp, scu_base + 8);
+}
+
static unsigned int __init r8a7779_get_core_count(void)
{
void __iomem *scu_base = scu_base_addr();
@@ -85,7 +102,7 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
cpu = cpu_logical_map(cpu);
/* disable cache coherency */
- scu_power_mode(scu_base_addr(), 3);
+ modify_scu_cpu_psr(3 << (cpu * 8), 0);
if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
ch = r8a7779_ch_cpu[cpu];
@@ -128,7 +145,7 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
cpu = cpu_logical_map(cpu);
/* enable cache coherency */
- scu_power_mode(scu_base_addr(), 0);
+ modify_scu_cpu_psr(0, 3 << (cpu * 8));
if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
ch = r8a7779_ch_cpu[cpu];
@@ -141,13 +158,15 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
{
+ int cpu = cpu_logical_map(0);
+
scu_enable(scu_base_addr());
/* Map the reset vector (in headsmp.S) */
__raw_writel(__pa(shmobile_secondary_vector), AVECR);
/* enable cache coherency on CPU0 */
- scu_power_mode(scu_base_addr(), 0);
+ modify_scu_cpu_psr(0, 3 << (cpu * 8));
r8a7779_pm_init();
--
1.7.10.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 4/4] sh: clkfwk: fixup unsed variable warning
2012-11-13 3:10 [GIT PULL] Renesas ARM-based SoC for v3.8 #4 Simon Horman
` (2 preceding siblings ...)
2012-11-13 3:10 ` [PATCH 3/4] Revert "ARM: shmobile: r8a7779: " Simon Horman
@ 2012-11-13 3:10 ` Simon Horman
2012-11-13 12:50 ` [GIT PULL] Renesas ARM-based SoC for v3.8 #4 Arnd Bergmann
4 siblings, 0 replies; 6+ messages in thread
From: Simon Horman @ 2012-11-13 3:10 UTC (permalink / raw)
To: linux-arm-kernel
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas•com>
This patch solves above warning
${LINUX}/drivers/sh/clk/cpg.c:404:6: warning: \
unused variable 'val' [-Wunused-variable]
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas•com>
Signed-off-by: Simon Horman <horms@verge•net.au>
---
drivers/sh/clk/cpg.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c
index b3dc441..5aedcdf 100644
--- a/drivers/sh/clk/cpg.c
+++ b/drivers/sh/clk/cpg.c
@@ -401,7 +401,6 @@ static int fsidiv_enable(struct clk *clk)
static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
{
- u32 val;
int idx;
idx = (clk->parent->rate / rate) & 0xffff;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [GIT PULL] Renesas ARM-based SoC for v3.8 #4
2012-11-13 3:10 [GIT PULL] Renesas ARM-based SoC for v3.8 #4 Simon Horman
` (3 preceding siblings ...)
2012-11-13 3:10 ` [PATCH 4/4] sh: clkfwk: fixup unsed variable warning Simon Horman
@ 2012-11-13 12:50 ` Arnd Bergmann
4 siblings, 0 replies; 6+ messages in thread
From: Arnd Bergmann @ 2012-11-13 12:50 UTC (permalink / raw)
To: linux-arm-kernel
On Tuesday 13 November 2012, Simon Horman wrote:
> please consider the following SoC fixes for 3.8.
> Its a little embarrassing, but they all fix problems introduced
> in previous pull-requests for 3.8 that have been merged.
No problem at all, thanks for the quick follow-up!
> * The three Revert patches back-out secondary CPU initialisation
> changes from Bastian Hecht which he as advised me are incorrect
> and break secondary CPU initialisation.
>
> * The clkfwk patch from Morimoto-san resolves a build warning.
>
> This pull-request is based on the renesas/soc3 branch in the arm-soc tree.
Pulled into next/soc2, on top of the previous branch.
Arnd
^ permalink raw reply [flat|nested] 6+ messages in thread