From: will.deacon@arm•com (Will Deacon)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 2/5] iommu/arm-smmu: add support for PCI master devices
Date: Fri, 4 Jul 2014 09:13:31 +0100 [thread overview]
Message-ID: <20140704081331.GB23379@arm.com> (raw)
In-Reply-To: <3b9f2103f5c44958a74f1e594a58d58a@BL2PR03MB468.namprd03.prod.outlook.com>
On Fri, Jul 04, 2014 at 08:41:53AM +0100, Varun Sethi wrote:
> Hi Will,
Hey Varun,
> > Once Thierry's generic IOMMU binding is sorted, we should look at adding
> > support for the Stream ID description. Have you looked at that at all?
> >
> Yes, I have looked at the bindings. Would we need to represent the stream
> ids for PCI devices in the device tree? Why do we want to depend on the
> firmware to map the requestor id to the stream id? It can be handled using
> the APIs proposed by Alex Williamson. This is similar to IOMMU group
> determination, which is handled by the IOMMU driver.
Well, there could easily be a fixed mapping from the ID at the host controller
and the ID seem by the SMMU (e.g. two host controllers sharing an SMMU?). I
don't think walking the PCI buses can help you there.
The way I was thinking to handle this is that we express SID = RID +
offset. In the device-tree, we can then describe a range of RIDs on the host
controller, a single offset, and we get back a range of SIDs.
In the worst case scenario, each RID maps to a totally random SID, so then
you have a huge table describing the mapping. I *think* this is actually
unlikely, and if we ever see such a device we can either have a large
mapping or put it into C code for that specific SoC (if it's really huge).
FWIW: I believe that the ACPI folks are thinking along similar lines.
Will
next prev parent reply other threads:[~2014-07-04 8:13 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-30 10:52 [PATCH 0/5] iommu/arm-smmu: Updates for 3.17 Will Deacon
2014-06-30 10:52 ` [PATCH 1/5] iommu/arm-smmu: fix calculation of TCR.T0SZ Will Deacon
2014-06-30 10:52 ` [PATCH 2/5] iommu/arm-smmu: add support for PCI master devices Will Deacon
2014-07-03 14:22 ` Varun Sethi
2014-07-03 14:43 ` Will Deacon
2014-07-04 7:41 ` Varun Sethi
2014-07-04 8:13 ` Will Deacon [this message]
2014-07-09 13:26 ` Will Deacon
2014-07-09 14:13 ` Alex Williamson
2014-07-09 16:39 ` Will Deacon
2014-10-06 12:42 ` Will Deacon
2014-07-09 14:21 ` Varun Sethi
2014-06-30 10:52 ` [PATCH 3/5] iommu/arm-smmu: caps: add IOMMU_CAP_INTR_REMAP capability Will Deacon
2014-06-30 10:52 ` [PATCH 4/5] iommu/arm-smmu: remove support for chained SMMUs Will Deacon
2014-06-30 10:52 ` [PATCH 5/5] iommu/arm-smmu: prefer stage-1 mappings where we have a choice Will Deacon
2014-07-09 6:36 ` leizhen
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