From: catalin.marinas@arm•com (Catalin Marinas)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 6/6] arm64: Emulate CP15 Barrier instructions
Date: Wed, 27 Aug 2014 18:40:01 +0100 [thread overview]
Message-ID: <20140827174001.GI13850@arm.com> (raw)
In-Reply-To: <1409048930-21598-7-git-send-email-punit.agrawal@arm.com>
On Tue, Aug 26, 2014 at 11:28:50AM +0100, Punit Agrawal wrote:
> diff --git a/arch/arm64/kernel/v7_obsolete.c b/arch/arm64/kernel/v7_obsolete.c
> index e9427cb..ed77889 100644
> --- a/arch/arm64/kernel/v7_obsolete.c
> +++ b/arch/arm64/kernel/v7_obsolete.c
> @@ -227,6 +227,94 @@ static void __init swp_emulation_init(void)
> pr_notice("Registered SWP/SWPB emulation handler\n");
> }
>
> +static atomic_t cp15_barrier_count;
Should we add counters for each barrier type? It may be more
informative.
> +/* data barrier */
> +static struct undef_hook cp15db_hook = {
> + .instr_mask = 0x0fff0fdf,
> + .instr_val = 0x0e070f9a,
> + .pstate_mask = COMPAT_PSR_MODE_MASK,
> + .pstate_val = COMPAT_PSR_MODE_USR,
> + .fn = cp15barrier_handler,
> +};
> +
> +/* instruction barrier */
> +static struct undef_hook cp15isb_hook = {
> + .instr_mask = 0x0fff0fff,
> + .instr_val = 0x0e070f95,
> + .pstate_mask = COMPAT_PSR_MODE_MASK,
> + .pstate_val = COMPAT_PSR_MODE_USR,
> + .fn = cp15barrier_handler,
> +};
It now crossed my mind that these CP15 barriers are valid in Thumb-2 as
well, same encoding. But we need the hook and the masks here to trap
them.
--
Catalin
next prev parent reply other threads:[~2014-08-27 17:40 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-26 10:28 [PATCH 0/6] Legacy instruction emulation for arm64 Punit Agrawal
2014-08-26 10:28 ` [PATCH 1/6] arm: Fix in-correct barrier usage in SWP{B} emulation Punit Agrawal
2014-08-26 13:04 ` Will Deacon
2014-08-27 16:40 ` Catalin Marinas
2014-08-27 17:05 ` Punit Agrawal
2014-08-26 10:28 ` [PATCH 2/6] arm64: Create arch debugfs directory Punit Agrawal
2014-08-26 10:28 ` [PATCH 3/6] arm64: Add support for hooks to handle undefined instructions Punit Agrawal
2014-08-26 13:13 ` Will Deacon
2014-08-26 14:21 ` Ard Biesheuvel
2014-08-26 14:30 ` Will Deacon
2014-08-27 16:47 ` Catalin Marinas
2014-08-27 16:51 ` Will Deacon
2014-08-26 14:56 ` Punit Agrawal
2014-08-26 18:14 ` Will Deacon
2014-08-27 16:58 ` Catalin Marinas
2014-08-26 10:28 ` [PATCH 4/6] arm64: Add AArch32 instruction set condition code checks Punit Agrawal
2014-08-26 10:28 ` [PATCH 5/6] arm64: Port SWP/SWPB emulation support from arm Punit Agrawal
2014-08-26 11:32 ` Arnd Bergmann
2014-08-26 12:25 ` Will Deacon
2014-08-26 13:26 ` Arnd Bergmann
2014-08-26 13:56 ` Will Deacon
2014-08-27 17:35 ` Punit Agrawal
2014-08-27 18:30 ` Arnd Bergmann
2014-08-28 10:21 ` Punit Agrawal
2014-08-27 17:29 ` Catalin Marinas
2014-08-26 10:28 ` [PATCH 6/6] arm64: Emulate CP15 Barrier instructions Punit Agrawal
2014-08-26 13:16 ` Will Deacon
2014-08-27 17:40 ` Catalin Marinas [this message]
2014-08-28 9:34 ` Punit Agrawal
2014-08-28 9:42 ` Catalin Marinas
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