* [PATCH 1/7] PCI: aardvark: fix logic in PCI configuration read/write functions
2017-09-08 9:53 [PATCH 0/7] PCI: aardvark: improve compatibility with PCI devices Thomas Petazzoni
@ 2017-09-08 9:53 ` Thomas Petazzoni
2017-09-08 9:53 ` [PATCH 2/7] PCI: aardvark: set PIO_ADDR_LS correctly in advk_pcie_rd_conf() Thomas Petazzoni
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Thomas Petazzoni @ 2017-09-08 9:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Victor Gu <xigu@marvell•com>
The PCI configuration space read/write functions were special casing
the situation where PCI_SLOT(devfn) != 0, and returned
PCIBIOS_DEVICE_NOT_FOUND in this case.
However, will this is what is intended for the root bus, it is not
intended for the child busses, as it prevents discovering devices with
PCI_SLOT(x) != 0. Therefore, we return PCIBIOS_DEVICE_NOT_FOUND only
if we're on the root bus.
Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc: <stable@vger•kernel.org>
Signed-off-by: Victor Gu <xigu@marvell•com>
Reviewed-by: Wilson Ding <dingwei@marvell•com>
Reviewed-by: Nadav Haklai <nadavh@marvell•com>
[Thomas: tweak commit log.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons•com>
---
drivers/pci/host/pci-aardvark.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 5fb9b620ac78..582d75f864e3 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -441,7 +441,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
u32 reg;
int ret;
- if (PCI_SLOT(devfn) != 0) {
+ if ((bus->number == pcie->root_bus_nr) && (PCI_SLOT(devfn) != 0)) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
@@ -495,7 +495,7 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
int offset;
int ret;
- if (PCI_SLOT(devfn) != 0)
+ if ((bus->number == pcie->root_bus_nr) && (PCI_SLOT(devfn) != 0))
return PCIBIOS_DEVICE_NOT_FOUND;
if (where % size)
--
2.13.5
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 2/7] PCI: aardvark: set PIO_ADDR_LS correctly in advk_pcie_rd_conf()
2017-09-08 9:53 [PATCH 0/7] PCI: aardvark: improve compatibility with PCI devices Thomas Petazzoni
2017-09-08 9:53 ` [PATCH 1/7] PCI: aardvark: fix logic in PCI configuration read/write functions Thomas Petazzoni
@ 2017-09-08 9:53 ` Thomas Petazzoni
2017-09-08 9:53 ` [PATCH 3/7] PCI: aardvark: set host and device to the same MAX payload size Thomas Petazzoni
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Thomas Petazzoni @ 2017-09-08 9:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Victor Gu <xigu@marvell•com>
When setting the PIO_ADDR_LS register during a configuration read, we
were properly passing the device number, function number and register
number, but not the bus number, causing issues when reading the
configuration of PCIe devices.
Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc: <stable@vger•kernel.org>
Signed-off-by: Victor Gu <xigu@marvell•com>
Reviewed-by: Wilson Ding <dingwei@marvell•com>
Reviewed-by: Nadav Haklai <nadavh@marvell•com>
[Thomas: tweak commit log.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons•com>
---
drivers/pci/host/pci-aardvark.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 582d75f864e3..68ff10e17c74 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -460,7 +460,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
advk_writel(pcie, reg, PIO_CTRL);
/* Program the address registers */
- reg = PCIE_BDF(devfn) | PCIE_CONF_REG(where);
+ reg = PCIE_CONF_ADDR(bus->number, devfn, where);
advk_writel(pcie, reg, PIO_ADDR_LS);
advk_writel(pcie, 0, PIO_ADDR_MS);
--
2.13.5
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 3/7] PCI: aardvark: set host and device to the same MAX payload size
2017-09-08 9:53 [PATCH 0/7] PCI: aardvark: improve compatibility with PCI devices Thomas Petazzoni
2017-09-08 9:53 ` [PATCH 1/7] PCI: aardvark: fix logic in PCI configuration read/write functions Thomas Petazzoni
2017-09-08 9:53 ` [PATCH 2/7] PCI: aardvark: set PIO_ADDR_LS correctly in advk_pcie_rd_conf() Thomas Petazzoni
@ 2017-09-08 9:53 ` Thomas Petazzoni
2017-09-08 9:53 ` [PATCH 4/7] PCI: aardvark: use isr1 instead of isr0 interrupt in legacy irq mode Thomas Petazzoni
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Thomas Petazzoni @ 2017-09-08 9:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Victor Gu <xigu@marvell•com>
Since the Aardvark does not implement a PCIe root bus, the Linux PCIe
subsystem will not align the MAX payload size between the host and the
device. This patch ensures that the host and device have the same MAX
payload size, fixing a number of problems with various PCIe devices.
This is part of fixing bug
https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
reported as the user to be important to get a Intel 7260 mini-PCIe
WiFi card working.
Fixes: Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Signed-off-by: Victor Gu <xigu@marvell•com>
Reviewed-by: Evan Wang <xswang@marvell•com>
Reviewed-by: Nadav Haklai <nadavh@marvell•com>
[Thomas: tweak commit log.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons•com>
---
drivers/pci/host/pci-aardvark.c | 60 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 68ff10e17c74..e361c673732f 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -30,8 +30,10 @@
#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
+#define PCIE_CORE_MPS_UNIT_BYTE 128
#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
#define PCIE_CORE_LINK_TRAINING BIT(5)
@@ -298,7 +300,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
/* Set PCIe Device Control and Status 1 PF0 register */
reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
+ PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
@@ -880,6 +883,58 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
return err;
}
+static int advk_pcie_find_smpss(struct pci_dev *dev, void *data)
+{
+ u8 *smpss = data;
+
+ if (!dev)
+ return 0;
+
+ if (!pci_is_pcie(dev))
+ return 0;
+
+ if (*smpss > dev->pcie_mpss)
+ *smpss = dev->pcie_mpss;
+
+ return 0;
+}
+
+static int advk_pcie_bus_configure_mps(struct pci_dev *dev, void *data)
+{
+ int mps;
+
+ if (!dev)
+ return 0;
+
+ if (!pci_is_pcie(dev))
+ return 0;
+
+ mps = PCIE_CORE_MPS_UNIT_BYTE << *(u8 *)data;
+ pcie_set_mps(dev, mps);
+
+ return 0;
+}
+
+static void advk_pcie_configure_mps(struct pci_bus *bus, struct advk_pcie *pcie)
+{
+ u8 smpss = PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ;
+ u32 reg;
+
+ /* Find the minimal supported MAX payload size */
+ advk_pcie_find_smpss(bus->self, &smpss);
+ pci_walk_bus(bus, advk_pcie_find_smpss, &smpss);
+
+ /* Configure RC MAX payload size */
+ reg = advk_readl(pcie, PCIE_CORE_DEV_CTRL_STATS_REG);
+ reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
+ reg |= smpss << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT;
+ advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
+
+ /* Configure device MAX payload size */
+ advk_pcie_bus_configure_mps(bus->self, &smpss);
+ pci_walk_bus(bus, advk_pcie_bus_configure_mps, &smpss);
+}
+
static int advk_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -951,6 +1006,9 @@ static int advk_pcie_probe(struct platform_device *pdev)
list_for_each_entry(child, &bus->children, node)
pcie_bus_configure_settings(child);
+ /* Configure the MAX pay load size */
+ advk_pcie_configure_mps(bus, pcie);
+
pci_bus_add_devices(bus);
return 0;
}
--
2.13.5
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 4/7] PCI: aardvark: use isr1 instead of isr0 interrupt in legacy irq mode
2017-09-08 9:53 [PATCH 0/7] PCI: aardvark: improve compatibility with PCI devices Thomas Petazzoni
` (2 preceding siblings ...)
2017-09-08 9:53 ` [PATCH 3/7] PCI: aardvark: set host and device to the same MAX payload size Thomas Petazzoni
@ 2017-09-08 9:53 ` Thomas Petazzoni
2017-09-08 9:53 ` [PATCH 5/7] PCI: aardvark: disable LOS state by default Thomas Petazzoni
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Thomas Petazzoni @ 2017-09-08 9:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Victor Gu <xigu@marvell•com>
The Aardvark has two interrupts sets:
- first set is bit[23:16] of PCIe ISR 0 register(RD0074840h)
- second set is bit[11:8] of PCIe ISR 1 register(RD0074848h)
Only one set should be used, while another set should be masked.
The second set, ISR1, is more advanced, the Legacy INT_X status bit is
asserted once Assert_INTX message is received, and de-asserted after
Deassert_INTX message is received. Therefore, it matches what the
driver is currently doing in the ->irq_mask() and ->irq_unmask()
functions. The ISR0 requires additional work to deassert the
interrupt, which the driver doesn't do currently.
This commit resolves a number of issues with legacy interrupts.
This is part of fixing bug
https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
reported as the user to be important to get a Intel 7260 mini-PCIe
WiFi card working.
Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Signed-off-by: Victor Gu <xigu@marvell•com>
Reviewed-by: Evan Wang <xswang@marvell•com>
Reviewed-by: Nadav Haklai <nadavh@marvell•com>
[Thomas: tweak commit log.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons•com>
---
drivers/pci/host/pci-aardvark.c | 41 ++++++++++++++++++++++++-----------------
1 file changed, 24 insertions(+), 17 deletions(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index e361c673732f..4a563d8526ae 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -105,7 +105,8 @@
#define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
#define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
#define PCIE_ISR1_FLUSH BIT(5)
-#define PCIE_ISR1_ALL_MASK GENMASK(5, 4)
+#define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
+#define PCIE_ISR1_ALL_MASK GENMASK(11, 4)
#define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
#define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
#define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
@@ -616,9 +617,9 @@ static void advk_pcie_irq_mask(struct irq_data *d)
irq_hw_number_t hwirq = irqd_to_hwirq(d);
u32 mask;
- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
- mask |= PCIE_ISR0_INTX_ASSERT(hwirq);
- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
+ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+ mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
+ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
}
static void advk_pcie_irq_unmask(struct irq_data *d)
@@ -627,9 +628,9 @@ static void advk_pcie_irq_unmask(struct irq_data *d)
irq_hw_number_t hwirq = irqd_to_hwirq(d);
u32 mask;
- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
- mask &= ~PCIE_ISR0_INTX_ASSERT(hwirq);
- advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
+ mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+ mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
+ advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
}
static int advk_pcie_irq_map(struct irq_domain *h,
@@ -772,29 +773,35 @@ static void advk_pcie_handle_msi(struct advk_pcie *pcie)
static void advk_pcie_handle_int(struct advk_pcie *pcie)
{
- u32 val, mask, status;
+ u32 isr0_val, isr0_mask, isr0_status;
+ u32 isr1_val, isr1_mask, isr1_status;
int i, virq;
- val = advk_readl(pcie, PCIE_ISR0_REG);
- mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
- status = val & ((~mask) & PCIE_ISR0_ALL_MASK);
+ isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
+ isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
+ isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
- if (!status) {
- advk_writel(pcie, val, PCIE_ISR0_REG);
+ isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
+ isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
+ isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
+
+ if (!isr0_status && !isr1_status) {
+ advk_writel(pcie, isr0_val, PCIE_ISR0_REG);
+ advk_writel(pcie, isr1_val, PCIE_ISR1_REG);
return;
}
/* Process MSI interrupts */
- if (status & PCIE_ISR0_MSI_INT_PENDING)
+ if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
advk_pcie_handle_msi(pcie);
/* Process legacy interrupts */
for (i = 0; i < LEGACY_IRQ_NUM; i++) {
- if (!(status & PCIE_ISR0_INTX_ASSERT(i)))
+ if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
continue;
- advk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i),
- PCIE_ISR0_REG);
+ advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
+ PCIE_ISR1_REG);
virq = irq_find_mapping(pcie->irq_domain, i);
generic_handle_irq(virq);
--
2.13.5
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 5/7] PCI: aardvark: disable LOS state by default
2017-09-08 9:53 [PATCH 0/7] PCI: aardvark: improve compatibility with PCI devices Thomas Petazzoni
` (3 preceding siblings ...)
2017-09-08 9:53 ` [PATCH 4/7] PCI: aardvark: use isr1 instead of isr0 interrupt in legacy irq mode Thomas Petazzoni
@ 2017-09-08 9:53 ` Thomas Petazzoni
2017-09-08 9:53 ` [PATCH 6/7] PCI: aardvark: fix PCIe max read request size setting Thomas Petazzoni
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Thomas Petazzoni @ 2017-09-08 9:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Victor Gu <xigu@marvell•com>
Some PCIe devices do not support LOS, and will cause timeouts if the
root complex forces the LOS state. This patch disables the LOS state
by default.
This is part of fixing bug
https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
reported as the user to be important to get a Intel 7260 mini-PCIe
WiFi card working.
Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Signed-off-by: Victor Gu <xigu@marvell•com>
Reviewed-by: Evan Wang <xswang@marvell•com>
Reviewed-by: Nadav Haklai <nadavh@marvell•com>
[Thomas: tweak commit log.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons•com>
---
drivers/pci/host/pci-aardvark.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 4a563d8526ae..461517a87eca 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -369,8 +369,7 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
advk_pcie_wait_for_link(pcie);
- reg = PCIE_CORE_LINK_L0S_ENTRY |
- (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
+ reg = (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
--
2.13.5
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 6/7] PCI: aardvark: fix PCIe max read request size setting
2017-09-08 9:53 [PATCH 0/7] PCI: aardvark: improve compatibility with PCI devices Thomas Petazzoni
` (4 preceding siblings ...)
2017-09-08 9:53 ` [PATCH 5/7] PCI: aardvark: disable LOS state by default Thomas Petazzoni
@ 2017-09-08 9:53 ` Thomas Petazzoni
2017-09-08 9:53 ` [PATCH 7/7] PCI: aardvark: define IRQ related hooks in pci_host_bridge Thomas Petazzoni
2017-09-25 14:41 ` [PATCH 0/7] PCI: aardvark: improve compatibility with PCI devices Thomas Petazzoni
7 siblings, 0 replies; 9+ messages in thread
From: Thomas Petazzoni @ 2017-09-08 9:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Evan Wang <xswang@marvell•com>
There is an obvious typo issue in the definition of the PCIe maximum
read request size: a bit shift is directly used as a value, while it
should be used to shift the correct value.
This is part of fixing bug
https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
reported as the user to be important to get a Intel 7260 mini-PCIe
WiFi card working.
Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Signed-off-by: Evan Wang <xswang@marvell•com>
Reviewed-by: Victor Gu <xigu@marvell•com>
Reviewed-by: Nadav Haklai <nadavh@marvell•com>
[Thomas: tweak commit log.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons•com>
---
drivers/pci/host/pci-aardvark.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 461517a87eca..6d6a2ae35481 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -33,6 +33,7 @@
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
#define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
+#define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
#define PCIE_CORE_MPS_UNIT_BYTE 128
#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
@@ -304,7 +305,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
(PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
- PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
+ PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
/* Program PCIe Control 2 to disable strict ordering */
--
2.13.5
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 7/7] PCI: aardvark: define IRQ related hooks in pci_host_bridge
2017-09-08 9:53 [PATCH 0/7] PCI: aardvark: improve compatibility with PCI devices Thomas Petazzoni
` (5 preceding siblings ...)
2017-09-08 9:53 ` [PATCH 6/7] PCI: aardvark: fix PCIe max read request size setting Thomas Petazzoni
@ 2017-09-08 9:53 ` Thomas Petazzoni
2017-09-25 14:41 ` [PATCH 0/7] PCI: aardvark: improve compatibility with PCI devices Thomas Petazzoni
7 siblings, 0 replies; 9+ messages in thread
From: Thomas Petazzoni @ 2017-09-08 9:53 UTC (permalink / raw)
To: linux-arm-kernel
Commit 769b461fc0c0 ("arm64: PCI: Drop DT IRQ allocation from
pcibios_alloc_irq()") was assuming all PCI host controller drivers had
been converted to use ->map_irq(), but that wasn't the case:
pci-aardvark had not been converted. Due to this, it broke the support
for legacy PCI interrupts when using the pci-aardvark driver (used on
Marvell Armada 3720 platforms).
In order to fix this, we make sure the ->map_irq and ->swizzle_irq
fields of pci_host_bridge are properly filled in.
Fixes: 769b461fc0c0 ("arm64: PCI: Drop DT IRQ allocation from pcibios_alloc_irq()")
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons•com>
Cc: <stable@vger•kernel.org> # v4.13+
---
drivers/pci/host/pci-aardvark.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c
index 6d6a2ae35481..f682650bf037 100644
--- a/drivers/pci/host/pci-aardvark.c
+++ b/drivers/pci/host/pci-aardvark.c
@@ -999,6 +999,8 @@ static int advk_pcie_probe(struct platform_device *pdev)
bridge->sysdata = pcie;
bridge->busnr = 0;
bridge->ops = &advk_pcie_ops;
+ bridge->map_irq = of_irq_parse_and_map_pci;
+ bridge->swizzle_irq = pci_common_swizzle;
ret = pci_scan_root_bus_bridge(bridge);
if (ret < 0) {
--
2.13.5
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 0/7] PCI: aardvark: improve compatibility with PCI devices
2017-09-08 9:53 [PATCH 0/7] PCI: aardvark: improve compatibility with PCI devices Thomas Petazzoni
` (6 preceding siblings ...)
2017-09-08 9:53 ` [PATCH 7/7] PCI: aardvark: define IRQ related hooks in pci_host_bridge Thomas Petazzoni
@ 2017-09-25 14:41 ` Thomas Petazzoni
7 siblings, 0 replies; 9+ messages in thread
From: Thomas Petazzoni @ 2017-09-25 14:41 UTC (permalink / raw)
To: linux-arm-kernel
Hello Bjorn,
On Fri, 8 Sep 2017 11:53:41 +0200, Thomas Petazzoni wrote:
> This patch series brings a number of fixes to the pci-aardvark driver
> that allows a much larger number of PCIe devices to be used.
>
> It fixes kernel bug
> https://bugzilla.kernel.org/show_bug.cgi?id=196339, and has been
> tested with an IGB NIC and a Marvell SATA PCIe card, which were not
> working previously.
>
> They should be taken for the 4.14 cycle, as they are all bug fixes.
Do you have some feedback about this series? It fixes some important
problems (reported by users), so it would be nice to have it in 4.14.
Thanks a lot!
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 9+ messages in thread