[PATCH v3 08/12] ARM: mstar: Add Armv7 base dtsi

From: Daniel Palmer <daniel@0x0f•com>
To: linux-kernel@vger•kernel.org
Cc: Linus Walleij <linus.walleij@linaro•org>,
	Masahiro Yamada <yamada.masahiro@socionext•com>,
	Daniel Palmer <daniel@thingy•jp>,
	Benjamin Gaignard <benjamin.gaignard@linaro•org>,
	Sam Ravnborg <sam@ravnborg•org>, Ard Biesheuvel <ardb@kernel•org>,
	Stephan Gerhold <stephan@gerhold•net>,
	Jonathan Corbet <corbet@lwn•net>,
	Mauro Carvalho Chehab <mchehab+huawei@kernel•org>,
	Heiko Stuebner <heiko.stuebner@theobroma-systems•com>,
	daniel@0x0f•com, Russell King <linux@armlinux•org.uk>,
	Bartosz Golaszewski <bgolaszewski@baylibre•com>,
	Joel Stanley <joel@jms•id.au>,
	Nathan Huckleberry <nhuck15@gmail•com>,
	devicetree@vger•kernel.org, Arnd Bergmann <arnd@arndb•de>,
	allen <allen.chen@ite•com.tw>, Will Deacon <will@kernel•org>,
	Lubomir Rintel <lkundrak@v3•sk>, Rob Herring <robh+dt@kernel•org>,
	Gregory Fong <gregory.0xf0@gmail•com>,
	Doug Anderson <armlinux@m•disordat.com>,
	Nathan Chancellor <natechancellor@gmail•com>,
	linux-arm-kernel@lists•infradead.org,
	Greg Kroah-Hartman <gregkh@linuxfoundation•org>,
	afaerber@suse•de, Mark Brown <broonie@kernel•org>,
	Marc Zyngier <maz@kernel•org>,
	"David S. Miller" <davem@davemloft•net>,
	Mike Rapoport <rppt@kernel•org>
Subject: [PATCH v3 08/12] ARM: mstar: Add Armv7 base dtsi
Date: Fri, 12 Jun 2020 22:00:08 +0900	[thread overview]
Message-ID: <20200612130032.3905240-9-daniel@0x0f.com> (raw)
In-Reply-To: <20200612130032.3905240-1-daniel@0x0f.com>

Adds initial dtsi for the base MStar/Sigmastar Armv7 SoCs.

These SoCs have very similar memory maps and this will avoid
duplicating nodes across multiple dtsis.

Signed-off-by: Daniel Palmer <daniel@0x0f•com>
---
 MAINTAINERS                     |  1 +
 arch/arm/boot/dts/mstar-v7.dtsi | 83 +++++++++++++++++++++++++++++++++
 2 files changed, 84 insertions(+)
 create mode 100644 arch/arm/boot/dts/mstar-v7.dtsi

diff --git a/MAINTAINERS b/MAINTAINERS
index 4bd57bbdddb0..00de66458e53 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2116,6 +2116,7 @@ L:	linux-arm-kernel@lists•infradead.org (moderated for non-subscribers)
 S:	Maintained
 W:	http://linux-chenxing.org/
 F:	Documentation/devicetree/bindings/arm/mstar.yaml
+F:	arch/arm/boot/dts/mstar-v7.dtsi
 F:	arch/arm/mach-mstar/
 
 ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
new file mode 100644
index 000000000000..3b99bb435bb5
--- /dev/null
+++ b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2020 thingy.jp.
+ * Author: Daniel Palmer <daniel@thingy•jp>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x0>;
+		};
+	};
+
+	arch_timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
+				| IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
+				| IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
+				| IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
+				| IRQ_TYPE_LEVEL_LOW)>;
+		/*
+		 * we shouldn't need this but the vendor
+		 * u-boot is broken
+		 */
+		clock-frequency = <6000000>;
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x16001000 0x16001000 0x00007000>,
+			 <0x1f000000 0x1f000000 0x00400000>;
+
+		gic: interrupt-controller@16001000 {
+			compatible = "arm,cortex-a7-gic";
+			reg = <0x16001000 0x1000>,
+			      <0x16002000 0x2000>,
+			      <0x16004000 0x2000>,
+			      <0x16006000 0x2000>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2)
+					| IRQ_TYPE_LEVEL_LOW)>;
+		};
+
+		riu: bus@1f000000 {
+			compatible = "simple-bus";
+			reg = <0x1f000000 0x00400000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x1f000000 0x00400000>;
+
+			l3bridge: l3bridge@204400 {
+				compatible = "mstar,l3bridge";
+				reg = <0x204400 0x200>;
+			};
+
+			pm_uart: uart@221000 {
+				compatible = "ns16550a";
+				reg = <0x221000 0x100>;
+				reg-shift = <3>;
+				clock-frequency = <172000000>;
+				status = "disabled";
+			};
+		};
+	};
+};
-- 
2.27.0.rc0


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