From: Qinxin Xia <xiaqinxin@huawei•com>
To: <robin.murphy@arm•com>, <nicolinc@nvidia•com>, <will@kernel•org>,
<jpb@kernel•org>
Cc: <linux-arm-kernel@lists•infradead.org>, <iommu@lists•linux.dev>,
<xiaqinxin@huawei•com>, <wangzhou1@hisilicon•com>,
<prime.zeng@hisilicon•com>, <fanghao11@huawei•com>,
<jonathan.cameron@huawei•com>, <wuyifan50@huawei•com>,
<linuxarm@huawei•com>
Subject: [RFC PATCH v2 2/5] iommu/arm-smmu-v3: Add register display to debugfs
Date: Sat, 28 Mar 2026 18:17:03 +0800 [thread overview]
Message-ID: <20260328101706.3448655-3-xiaqinxin@huawei.com> (raw)
In-Reply-To: <20260328101706.3448655-1-xiaqinxin@huawei.com>
Add register display functionality to debugfs.This allows reading
and displaying key SMMU register values including control registers
and queue pointers.
The registers file shows:
- CR0, CR1, CR2 control registers
- Command and Event queue pointers
Signed-off-by: Qinxin Xia <xiaqinxin@huawei•com>
---
.../arm/arm-smmu-v3/arm-smmu-v3-debugfs.c | 78 ++++++++++++++++++-
1 file changed, 77 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-debugfs.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-debugfs.c
index c764b28e5cfb..cfd296aebc9f 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-debugfs.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-debugfs.c
@@ -5,13 +5,18 @@
* Directory Structure:
* /sys/kernel/debug/iommu/arm_smmu_v3/
* └── smmu<ioaddr>/
- * └── capabilities # SMMU feature capabilities and configuration
+ * ├── capabilities # SMMU feature capabilities and configuration
+ * └── registers # SMMU Key registers
*
* The capabilities file provides detailed information about:
* - translation stage support (Stage1/Stage2)
* - System coherency, ATS, and PRI feature availability
* - Stream table size and command/event queue depths
*
+ * The registers display provides crucial visibility into:
+ * - CR0, CR1, CR2 control registers
+ * - Command and Event queue pointers
+ *
* Copyright (C) 2026 HiSilicon Limited.
* Author: Qinxin Xia <xiaqinxin@huawei•com>
*/
@@ -89,6 +94,74 @@ static const struct file_operations smmu_debugfs_capabilities_fops = {
.release = smmu_debugfs_capabilities_release,
};
+/**
+ * smmu_debugfs_registers_show() - Display SMMU register values
+ * @seq: seq_file to write to
+ *
+ * Errors are reported via seq_puts, the function always returns 0
+ */
+static int smmu_debugfs_registers_show(struct seq_file *seq, void *unused)
+{
+ struct arm_smmu_device *smmu = seq->private;
+ void __iomem *base;
+
+ if (!smmu || !smmu->base) {
+ seq_puts(seq, "SMMU not available\n");
+ return 0;
+ }
+
+ base = smmu->base;
+
+ seq_puts(seq, "SMMUv3 Key Registers:\n");
+
+ /* 32-bit control registers */
+ seq_printf(seq, "CR0: 0x%08x\n", readl_relaxed(base + ARM_SMMU_CR0));
+ seq_printf(seq, "CR1: 0x%08x\n", readl_relaxed(base + ARM_SMMU_CR1));
+ seq_printf(seq, "CR2: 0x%08x\n", readl_relaxed(base + ARM_SMMU_CR2));
+
+ /* 32-bit queue pointer registers */
+ seq_printf(seq, "CMDQ_PROD: 0x%08x\n",
+ readl_relaxed(base + ARM_SMMU_CMDQ_PROD));
+ seq_printf(seq, "CMDQ_CONS: 0x%08x\n",
+ readl_relaxed(base + ARM_SMMU_CMDQ_CONS));
+ seq_printf(seq, "EVTQ_PROD: 0x%08x\n",
+ readl_relaxed(base + ARM_SMMU_EVTQ_PROD));
+ seq_printf(seq, "EVTQ_CONS: 0x%08x\n",
+ readl_relaxed(base + ARM_SMMU_EVTQ_CONS));
+
+ return 0;
+}
+
+static int smmu_debugfs_registers_open(struct inode *inode, struct file *file)
+{
+ struct arm_smmu_device *smmu = inode->i_private;
+
+ if (!smmu || !get_device(smmu->dev))
+ return -ENODEV;
+
+ return single_open(file, smmu_debugfs_registers_show, smmu);
+}
+
+static int smmu_debugfs_registers_release(struct inode *inode, struct file *file)
+{
+ struct seq_file *seq = file->private_data;
+ struct arm_smmu_device *smmu = seq->private;
+
+ single_release(inode, file);
+ if (smmu)
+ put_device(smmu->dev);
+
+ return 0;
+}
+
+static const struct file_operations smmu_debugfs_registers_fops = {
+ .owner = THIS_MODULE,
+ .open = smmu_debugfs_registers_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = smmu_debugfs_registers_release,
+};
+
/**
* arm_smmu_debugfs_setup() - Initialize debugfs for SMMU device
* @smmu: SMMU device to setup debugfs for
@@ -134,6 +207,9 @@ int arm_smmu_debugfs_setup(struct arm_smmu_device *smmu, const char *name)
debugfs_create_file("capabilities", 0444, smmu_dir, smmu,
&smmu_debugfs_capabilities_fops);
+ debugfs_create_file("registers", 0444, smmu_dir, smmu,
+ &smmu_debugfs_registers_fops);
+
dev_dbg(smmu->dev, "debugfs initialized for %s\n", name);
return 0;
}
--
2.33.0
next prev parent reply other threads:[~2026-03-28 10:17 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-28 10:17 [RFC PATCH v2 0/5] Add debugfs support for ARM SMMUv3 Qinxin Xia
2026-03-28 10:17 ` [RFC PATCH v2 1/5] iommu/arm-smmu-v3: Add basic debugfs framework Qinxin Xia
2026-03-30 10:46 ` Nicolin Chen
2026-04-02 3:50 ` Qinxin Xia
2026-03-28 10:17 ` Qinxin Xia [this message]
2026-03-30 11:25 ` [RFC PATCH v2 2/5] iommu/arm-smmu-v3: Add register display to debugfs Nicolin Chen
2026-03-28 10:17 ` [RFC PATCH v2 3/5] iommu/arm-smmu-v3: Add Stream Table Entry " Qinxin Xia
2026-04-04 5:43 ` Nicolin Chen
2026-03-28 10:17 ` [RFC PATCH v2 4/5] iommu/arm-smmu-v3: Add device symlink in stream table debugfs Qinxin Xia
2026-03-28 10:17 ` [RFC PATCH v2 5/5] iommu/arm-smmu-v3: Add Context Descriptor display to debugfs Qinxin Xia
2026-05-20 6:37 ` [PATCH 0/5] Add debugfs support for ARM SMMUv3 Qinxin Xia
2026-05-20 6:37 ` [PATCH 1/5] iommu/arm-smmu-v3: Add basic debugfs framework Qinxin Xia
2026-05-27 0:41 ` Nicolin Chen
2026-05-20 6:37 ` [PATCH 2/5] iommu/arm-smmu-v3: Add register display to debugfs Qinxin Xia
2026-05-27 1:28 ` Nicolin Chen
2026-05-20 6:37 ` [PATCH 3/5] iommu/arm-smmu-v3: Add Stream Table Entry " Qinxin Xia
2026-05-27 2:18 ` Nicolin Chen
2026-05-27 2:43 ` Nicolin Chen
2026-05-20 6:37 ` [PATCH 4/5] iommu/arm-smmu-v3: Add device symlink in stream table debugfs Qinxin Xia
2026-05-20 6:37 ` [PATCH 5/5] iommu/arm-smmu-v3: Add Context Descriptor display to debugfs Qinxin Xia
2026-05-27 2:40 ` Nicolin Chen
2026-05-27 0:07 ` [PATCH 0/5] Add debugfs support for ARM SMMUv3 Nicolin Chen
-- strict thread matches above, loose matches on Subject: below --
2026-03-28 10:09 [RFC PATCH v2 " Qinxin Xia
2026-03-28 10:09 ` [RFC PATCH v2 2/5] iommu/arm-smmu-v3: Add register display to debugfs Qinxin Xia
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