From: Geetha sowjanya <gakula@marvell•com>
To: <linux-perf-users@vger•kernel.org>,
<linux-kernel@vger•kernel.org>,
<linux-arm-kernel@lists•infradead.org>,
<devicetree@vger•kernel.org>
Cc: <mark.rutland@arm•com>, <will@kernel•org>, <krzk+dt@kernel•org>
Subject: [PATCH v7 0/2] perf: marvell: Add CN20K DDR PMU support
Date: Wed, 27 May 2026 21:11:16 +0530 [thread overview]
Message-ID: <20260527154118.12884-1-gakula@marvell.com> (raw)
This series adds support for the DDR Performance Monitoring Unit (PMU)
present in Marvell CN20K SoCs.
The DDR PMU is part of the DRAM Subsystem (DSS) and provides hardware
counters to monitor DDR traffic and performance events. The block
implements eight programmable counters and two fixed-function counters
tracking DDR read and write activity, and is accessed via a dedicated
MMIO region.
CN20K is the successor to CN10K, and the DDR PMU hardware is functionally
equivalent to the CN10K implementation, with only minor differences in
register offsets and event mappings. To allow software to distinguish
between the two silicon variants, this series introduces a specific
"marvell,cn20k-ddr-pmu" compatible and extends the existing
marvell_cn10k_ddr_pmu driver to handle CN20K via variant-specific data.
Changes in v7:
- dt-bindings: dropped the CN20K DeviceTree example.
- perf: Handle ZQ sysfs IDs (62/63) in a dedicated switch case before the
DFI range so GCC does not see overlapping case labels and Odyssey IDs
58-61 no longer fall through into ZQ handling.
- perf: Resolve shared numeric IDs 58-61 inside the DFI case for CN20K vs
Odyssey (identical bitmap); extend programmable-event coverage to CAS
events (36-38) for CN20K sysfs.
- perf: On event_add failure from ddr_perf_get_event_bitmap, cancel the
hrtimer if needed and free the counter slot instead of returning with
partial setup.
- perf: For CN20K, zero CFG0 before writing ZQ to CFG1 and zero CFG1
before non-ZQ CFG0 so stale masks do not combine across banks.
Changes in v6:
- dt-bindings: Document CN20K in the existing marvell-cn10k-ddr.yaml;
add maintainer, description, compatible enum entry, and a CN20K example
with unit-address aligned to reg.
- perf: Route CN20K ZQ events via dedicated sysfs IDs (62/63) and CFG1
programming; use (eventid - 42) for CFG1 bit positions and reject those IDs
on non-CN20K silicon.
- perf: Disambiguate CN20K perf width events (58-61) from Odyssey DFI events
at the same numeric IDs using an early CN20K branch and fallthrough into the
existing DFI + programmable-event path on Odyssey.
- perf: Run CN20K programmable counters through the same manual-mode / start
sequence as Odyssey.
Changes in v4:
- Fixed document file name.
Changes in v3:
- Expanded cover letter and commit message to better describe the DDR PMU
hardware and its relationship to CN10K
- Fixed the file name.
Changes in v2:
- Fixed YAML syntax error triggered by a tab character in the examples
section, which caused dt_binding_check to fail.
Changes in v1:
- Added a description field to the binding.
- Simplified the compatible property using 'const' instead of 'items/enum'.
- Updated the example node name to include a unit-address matching the reg base.
Signed-off-by: Geetha sowjanya <gakula@marvell•com>
Geetha sowjanya (2):
dt-bindings: perf: marvell: Extend CN10K DDR PMU binding for CN20K
perf: marvell: Add CN20K DDR PMU support
.../bindings/perf/marvell-cn10k-ddr.yaml | 18 +-
drivers/perf/marvell_cn10k_ddr_pmu.c | 197 ++++++++++++++++--
2 files changed, 200 insertions(+), 15 deletions(-)
--
2.25.1
next reply other threads:[~2026-05-27 15:41 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-27 15:41 Geetha sowjanya [this message]
2026-05-27 15:41 ` [PATCH v7 1/2] dt-bindings: perf: marvell: Add CN20K DDR PMU binding Geetha sowjanya
2026-05-28 7:49 ` Krzysztof Kozlowski
2026-05-27 15:41 ` [PATCH v7 2/2] perf: marvell: Add CN20K DDR PMU support Geetha sowjanya
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