From: Geetha sowjanya <gakula@marvell•com>
To: <linux-perf-users@vger•kernel.org>,
<linux-kernel@vger•kernel.org>,
<linux-arm-kernel@lists•infradead.org>,
<devicetree@vger•kernel.org>
Cc: <mark.rutland@arm•com>, <will@kernel•org>, <krzk+dt@kernel•org>
Subject: [PATCH v7 1/2] dt-bindings: perf: marvell: Add CN20K DDR PMU binding
Date: Wed, 27 May 2026 21:11:17 +0530 [thread overview]
Message-ID: <20260527154118.12884-2-gakula@marvell.com> (raw)
In-Reply-To: <20260527154118.12884-1-gakula@marvell.com>
Marvell CN20K SoCs integrate a DDR Performance Monitoring Unit (PMU)
associated with the DDR controller. The block provides hardware counters
to monitor DDR traffic and performance events and is accessed via a
dedicated MMIO region.
The CN20K DDR PMU is functionally equivalent to the CN10K DDR PMU, with
minor register offset differences.
Signed-off-by: Geetha sowjanya <gakula@marvell•com>
---
Changes in v7:
- Dropped the CN20K DeviceTree example.
Changes in v6:
- dt-bindings: Document CN20K in the existing marvell-cn10k-ddr.yaml;
add maintainer, description, compatible enum entry, and a CN20K example
with unit-address aligned to reg.
.../devicetree/bindings/perf/marvell-cn10k-ddr.yaml | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml
index a18dd0a8c43a..f2f0d6b61eac 100644
--- a/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml
+++ b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml
@@ -4,16 +4,22 @@
$id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Marvell CN10K DDR performance monitor
+title: Marvell CN10K / CN20K DDR performance monitor
+
+description:
+ Performance Monitoring Unit (PMU) for the DDR controller on Marvell
+ CN10K and CN20K SoCs. The block is accessed via a dedicated MMIO region.
maintainers:
- Bharat Bhushan <bbhushan2@marvell•com>
+ - Geetha sowjanya <gakula@marvell•com>
properties:
compatible:
items:
- enum:
- marvell,cn10k-ddr-pmu
+ - marvell,cn20k-ddr-pmu
reg:
maxItems: 1
--
2.25.1
next prev parent reply other threads:[~2026-05-27 15:41 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-27 15:41 [PATCH v7 0/2] perf: marvell: Add CN20K DDR PMU support Geetha sowjanya
2026-05-27 15:41 ` Geetha sowjanya [this message]
2026-05-28 7:49 ` [PATCH v7 1/2] dt-bindings: perf: marvell: Add CN20K DDR PMU binding Krzysztof Kozlowski
2026-05-27 15:41 ` [PATCH v7 2/2] perf: marvell: Add CN20K DDR PMU support Geetha sowjanya
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