From: joakim.zhang@cixtech•com
To: mturquette@baylibre•com, sboyd@kernel•org, bmasney@redhat•com,
robh@kernel•org, krzk+dt@kernel•org, conor+dt@kernel•org,
p.zabel@pengutronix•de, gary.yang@cixtech•com
Cc: cix-kernel-upstream@cixtech•com, linux-clk@vger•kernel.org,
devicetree@vger•kernel.org, linux-kernel@vger•kernel.org,
linux-arm-kernel@lists•infradead.org,
Joakim Zhang <joakim.zhang@cixtech•com>
Subject: [PATCH v2 2/5] reset: cix: add audss support to sky1 reset driver
Date: Fri, 5 Jun 2026 11:22:22 +0800 [thread overview]
Message-ID: <20260605032225.523669-3-joakim.zhang@cixtech.com> (raw)
In-Reply-To: <20260605032225.523669-1-joakim.zhang@cixtech.com>
From: Joakim Zhang <joakim.zhang@cixtech•com>
Extend the Sky1 reset controller driver for the AUDSS CRU syscon. The
AUDSS block provides sixteen active-low software reset bits in one
register for audio subsystem peripherals.
Add a device tree match for cix,sky1-audss-system-control and the
corresponding reset signal table in reset-sky1.c, reusing the existing
regmap-based reset ops used by the FCH and S5 system control variants.
Signed-off-by: Joakim Zhang <joakim.zhang@cixtech•com>
---
drivers/reset/reset-sky1.c | 36 ++++++++++++++++++++++++++++++++++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/reset/reset-sky1.c b/drivers/reset/reset-sky1.c
index 78e80a533c39..ff91ce93c16b 100644
--- a/drivers/reset/reset-sky1.c
+++ b/drivers/reset/reset-sky1.c
@@ -16,6 +16,7 @@
#include <dt-bindings/reset/cix,sky1-system-control.h>
#include <dt-bindings/reset/cix,sky1-s5-system-control.h>
+#include <dt-bindings/reset/cix,sky1-audss-system-control.h>
#define SKY1_RESET_SLEEP_MIN_US 50
#define SKY1_RESET_SLEEP_MAX_US 100
@@ -258,6 +259,34 @@ static const struct sky1_src_variant variant_sky1_fch = {
.signals_num = ARRAY_SIZE(sky1_src_fch_signals),
};
+enum {
+ AUDSS_SW_RST = 0x78,
+};
+
+static const struct sky1_src_signal sky1_audss_signals[SKY1_AUDSS_SW_RESET_NUM] = {
+ [AUDSS_I2S0_SW_RST_N] = { AUDSS_SW_RST, BIT(0) },
+ [AUDSS_I2S1_SW_RST_N] = { AUDSS_SW_RST, BIT(1) },
+ [AUDSS_I2S2_SW_RST_N] = { AUDSS_SW_RST, BIT(2) },
+ [AUDSS_I2S3_SW_RST_N] = { AUDSS_SW_RST, BIT(3) },
+ [AUDSS_I2S4_SW_RST_N] = { AUDSS_SW_RST, BIT(4) },
+ [AUDSS_I2S5_SW_RST_N] = { AUDSS_SW_RST, BIT(5) },
+ [AUDSS_I2S6_SW_RST_N] = { AUDSS_SW_RST, BIT(6) },
+ [AUDSS_I2S7_SW_RST_N] = { AUDSS_SW_RST, BIT(7) },
+ [AUDSS_I2S8_SW_RST_N] = { AUDSS_SW_RST, BIT(8) },
+ [AUDSS_I2S9_SW_RST_N] = { AUDSS_SW_RST, BIT(9) },
+ [AUDSS_WDT_SW_RST_N] = { AUDSS_SW_RST, BIT(10) },
+ [AUDSS_TIMER_SW_RST_N] = { AUDSS_SW_RST, BIT(11) },
+ [AUDSS_MB0_SW_RST_N] = { AUDSS_SW_RST, BIT(12) },
+ [AUDSS_MB1_SW_RST_N] = { AUDSS_SW_RST, BIT(13) },
+ [AUDSS_HDA_SW_RST_N] = { AUDSS_SW_RST, BIT(14) },
+ [AUDSS_DMAC_SW_RST_N] = { AUDSS_SW_RST, BIT(15) },
+};
+
+static const struct sky1_src_variant variant_sky1_audss = {
+ .signals = sky1_audss_signals,
+ .signals_num = ARRAY_SIZE(sky1_audss_signals),
+};
+
static struct sky1_src *to_sky1_src(struct reset_controller_dev *rcdev)
{
return container_of(rcdev, struct sky1_src, rcdev);
@@ -329,6 +358,8 @@ static int sky1_reset_probe(struct platform_device *pdev)
return -ENOMEM;
variant = of_device_get_match_data(dev);
+ if (!variant)
+ return -ENODEV;
sky1src->regmap = device_node_to_regmap(dev->of_node);
if (IS_ERR(sky1src->regmap)) {
@@ -347,8 +378,9 @@ static int sky1_reset_probe(struct platform_device *pdev)
}
static const struct of_device_id sky1_sysreg_of_match[] = {
- { .compatible = "cix,sky1-system-control", .data = &variant_sky1_fch},
- { .compatible = "cix,sky1-s5-system-control", .data = &variant_sky1},
+ { .compatible = "cix,sky1-system-control", .data = &variant_sky1_fch },
+ { .compatible = "cix,sky1-s5-system-control", .data = &variant_sky1 },
+ { .compatible = "cix,sky1-audss-system-control", .data = &variant_sky1_audss },
{},
};
MODULE_DEVICE_TABLE(of, sky1_sysreg_of_match);
--
2.50.1
next prev parent reply other threads:[~2026-06-05 3:24 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-05 3:22 [PATCH v2 0/5] Add Cix Sky1 AUDSS clock and reset support joakim.zhang
2026-06-05 3:22 ` [PATCH v2 1/5] dt-bindings: soc: cix,sky1-system-control: add audss system control joakim.zhang
2026-06-05 4:40 ` Rob Herring (Arm)
2026-06-05 3:22 ` joakim.zhang [this message]
2026-06-05 3:22 ` [PATCH v2 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller joakim.zhang
2026-06-05 3:22 ` [PATCH v2 4/5] clk: cix: add sky1 " joakim.zhang
2026-06-05 7:42 ` Philipp Zabel
2026-06-05 3:22 ` [PATCH v2 5/5] arm64: dts: cix: sky1: add audss system control joakim.zhang
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