From: gregory.clement@free-electrons•com (Gregory CLEMENT)
To: linux-arm-kernel@lists•infradead.org
Subject: [RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
Date: Fri, 10 Aug 2012 17:13:41 +0200 [thread overview]
Message-ID: <50252525.8050602@free-electrons.com> (raw)
In-Reply-To: <20120810144922.GH2066@mudshark.cambridge.arm.com>
On 08/10/2012 04:49 PM, Will Deacon wrote:
> On Wed, Aug 08, 2012 at 05:52:20PM +0100, Gregory CLEMENT wrote:
>> On 08/08/2012 06:30 PM, Gregory CLEMENT wrote:
>>> Yes indeed this SoC support LPAE.
>>
>> Well Armada XP supports LPAE but don't use any outer cache functions, he works
>> with the Aurora cache controller on 'system cache'.
>> Armada 370 uses this outer cache functions but doesn't support LPAE.
>
> Can the Armada 370 be configured to use the co-processor interface to the
> L2, or does only the Armada XP support that feature? What happens if you
> build a single zImage supporting both of the SoCs?
About L2 cache we already use the same kernel on Armada 370 and Armada XP
and the differences are in the device tree.
Now if I understood correctly what the LPAE involved, I guess we can't have
a kernel with LAPE running on Armada 370.
>
> Will
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
next prev parent reply other threads:[~2012-08-10 15:13 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-08 15:05 [RFC] Add support for Aurora L2 Cache Controller Gregory CLEMENT
2012-08-08 15:05 ` [RFC 1/6] arm: cache-l2x0: make outer_cache_fns a field of l2x0_of_data Gregory CLEMENT
2012-08-08 15:05 ` [RFC 2/6] arm: cache-l2x0: add an optional register to save/restore Gregory CLEMENT
2012-08-08 15:05 ` [RFC 5/6] arm: mvebu: add Aurora L2 Cache Controller to the DT Gregory CLEMENT
2012-08-08 15:06 ` [RFC 4/6] arm: mvebu: add L2 cache support Gregory CLEMENT
2012-08-08 15:06 ` [RFC 6/6] arm: l2x0: add aurora related properties to OF binding Gregory CLEMENT
2012-08-08 15:06 ` [RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl Gregory CLEMENT
2012-08-08 15:19 ` Will Deacon
2012-08-08 16:30 ` Gregory CLEMENT
2012-08-08 16:52 ` Gregory CLEMENT
2012-08-10 14:49 ` Will Deacon
2012-08-10 15:13 ` Gregory CLEMENT [this message]
2012-08-10 15:20 ` Will Deacon
2012-08-10 15:31 ` Gregory CLEMENT
2012-08-09 16:48 ` LPAE for outer caches functiopns (was Re: [RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl) Gregory CLEMENT
2012-08-09 16:49 ` [RFC 2 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl Gregory CLEMENT
2012-08-10 14:47 ` LPAE for outer caches functiopns (was Re: [RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl) Will Deacon
2012-08-10 15:02 ` Gregory CLEMENT
2012-08-13 10:44 ` Will Deacon
2012-08-08 15:16 ` [RFC] Add support for Aurora L2 Cache Controller Catalin Marinas
2012-08-21 7:29 ` Gregory CLEMENT
2012-08-08 16:22 ` Gregory CLEMENT
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=50252525.8050602@free-electrons.com \
--to=gregory.clement@free-electrons$(echo .)com \
--cc=linux-arm-kernel@lists$(echo .)infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox