[RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

From: gregory.clement@free-electrons•com (Gregory CLEMENT)
To: linux-arm-kernel@lists•infradead.org
Subject: [RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
Date: Fri, 10 Aug 2012 17:31:46 +0200	[thread overview]
Message-ID: <50252962.5090107@free-electrons.com> (raw)
In-Reply-To: <20120810152036.GK2066@mudshark.cambridge.arm.com>

On 08/10/2012 05:20 PM, Will Deacon wrote:
> On Fri, Aug 10, 2012 at 04:13:41PM +0100, Gregory CLEMENT wrote:
>> On 08/10/2012 04:49 PM, Will Deacon wrote:
>>> Can the Armada 370 be configured to use the co-processor interface to the
>>> L2, or does only the Armada XP support that feature? What happens if you
>>> build a single zImage supporting both of the SoCs?
>>
>> About L2 cache we already use the same kernel on Armada 370 and Armada XP
>> and the differences are in the device tree.
> 
> Right, but I wonder whether you can end up using both the outer_cache
> functions *and* the co-processor interface on the Armada XP by accident.

Well from what I know it should be possible to have both in the same time.
However we implement the support in a way that you won't have both in the
same time: if we use the "system cache" mode then we don't use any outer_cache
functions.

> Ideally, we'd just use the co-processor interface on all platforms and
> ignore the memory-mapped one. Is that possible on the 370?
> 
The 370 can't use the "system cache" mode (ie the co-processor).

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-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com