From: santosh.shilimkar@ti•com (Santosh Shilimkar)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v3 03/15] ARM: mcpm: introduce helpers for platform coherency exit/setup
Date: Fri, 1 Feb 2013 10:40:03 +0530 [thread overview]
Message-ID: <510B4E2B.1030104@ti.com> (raw)
In-Reply-To: <alpine.LFD.2.02.1301311210040.6300@xanadu.home>
On Thursday 31 January 2013 10:46 PM, Nicolas Pitre wrote:
> On Thu, 31 Jan 2013, Santosh Shilimkar wrote:
>
>> On Tuesday 29 January 2013 01:20 PM, Nicolas Pitre wrote:
>>> From: Dave Martin <dave.martin@linaro•org>
>>>
>>> This provides helper methods to coordinate between CPUs coming down
>>> and CPUs going up, as well as documentation on the used algorithms,
>>> so that cluster teardown and setup
>>> operations are not done for a cluster simultaneously.
>>>
>>> For use in the power_down() implementation:
>>> * __mcpm_cpu_going_down(unsigned int cluster, unsigned int cpu)
>>> * __mcpm_outbound_enter_critical(unsigned int cluster)
>>> * __mcpm_outbound_leave_critical(unsigned int cluster)
>>> * __mcpm_cpu_down(unsigned int cluster, unsigned int cpu)
>>>
>>> The power_up_setup() helper should do platform-specific setup in
>>> preparation for turning the CPU on, such as invalidating local caches
>>> or entering coherency. It must be assembler for now, since it must
>>> run before the MMU can be switched on. It is passed the affinity level
>>> which should be initialized.
>>>
>>> Because the mcpm_sync_struct content is looked-up and modified
>>> with the cache enabled or disabled depending on the code path, it is
>>> crucial to always ensure proper cache maintenance to update main memory
>>> right away. Therefore, any cached write must be followed by a cache
>>> clean operation and any cached read must be preceded by a cache
>>> invalidate operation (actually a cache flush i.e. clean+invalidate to
>>> avoid discarding possible concurrent writes) on the accessed memory.
>>>
>>> Also, in order to prevent a cached writer from interfering with an
>>> adjacent non-cached writer, we ensure each state variable is located to
>>> a separate cache line.
>>>
>>> Thanks to Nicolas Pitre and Achin Gupta for the help with this
>>> patch.
>>>
>>> Signed-off-by: Dave Martin <dave.martin@linaro•org>
>>> ---
>> [..]
>>
>>> diff --git a/arch/arm/common/mcpm_entry.c b/arch/arm/common/mcpm_entry.c
>>> index c8c0e2113e..2b83121966 100644
>>> --- a/arch/arm/common/mcpm_entry.c
>>> +++ b/arch/arm/common/mcpm_entry.c
>>> @@ -18,6 +18,7 @@
>>> #include <asm/proc-fns.h>
>>> #include <asm/cacheflush.h>
>>> #include <asm/idmap.h>
>>> +#include <asm/cputype.h>
>>>
>>> extern volatile unsigned long
>>> mcpm_entry_vectors[MAX_NR_CLUSTERS][MAX_CPUS_PER_CLUSTER];
>>>
>> [...]
>>
>>> +/*
>>> + * Ensure preceding writes to *p by other CPUs are visible to
>>> + * subsequent reads by this CPU. We must be careful not to
>>> + * discard data simultaneously written by another CPU, hence the
>>> + * usage of flush rather than invalidate operations.
>>> + */
>>> +static void __sync_range_r(volatile void *p, size_t size)
>>> +{
>>> + char *_p = (char *)p;
>>> +
>>> +#ifdef CONFIG_OUTER_CACHE
>>> + if (outer_cache.flush_range) {
>>> +
>> You don't need above #ifdef. In case of non-outer
>> cache the function pointer is null anyways.
>
> We do need the #ifdef, because if CONFIG_OUTER_CACHE is not selected
> then the outer_cache structure simply doesn't exist.
>
You are right. #ifdef in middle of the code looks bit ugly and hence
was thinking to avoid it.
>> /*
>>> + * Ensure dirty data migrated from other CPUs into our cache
>>> + * are cleaned out safely before the outer cache is cleaned:
>>> + */
>>> + __cpuc_clean_dcache_area(_p, size);
>>> +
>>> + /* Clean and invalidate stale data for *p from outer ... */
>>> + outer_flush_range(__pa(_p), __pa(_p + size));
>>> + }
>>> +#endif
>>> +
>>> + /* ... and inner cache: */
>>> + __cpuc_flush_dcache_area(_p, size);
>> This will be un-necessary when inner cache is available, no ?
>> May be you can re-arrange the code like below, unless and until
>> you would like to invalidate any speculative fetches during the
>> outer_flush_range()
>>
>> __cpuc_clean_dcache_area(_p, size);
>> if (outer_cache.flush_range)
>> outer_flush_range(__pa(_p), __pa(_p + size));
>
> As you said, the code is sequenced that way to get rid of potential
> speculative fetch that could happen right before L2 is flushed.
>
Thanks for clarifying it. It makes sense.
Regards,
Santosh
next prev parent reply other threads:[~2013-02-01 5:10 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-29 7:50 [PATCH v3 00/15] multi-cluster power management Nicolas Pitre
2013-01-29 7:50 ` [PATCH v3 01/15] ARM: multi-cluster PM: secondary kernel entry code Nicolas Pitre
2013-01-31 15:45 ` Santosh Shilimkar
2013-01-29 7:50 ` [PATCH v3 02/15] ARM: mcpm: introduce the CPU/cluster power API Nicolas Pitre
2013-01-31 15:55 ` Santosh Shilimkar
2013-01-29 7:50 ` [PATCH v3 03/15] ARM: mcpm: introduce helpers for platform coherency exit/setup Nicolas Pitre
2013-01-31 16:08 ` Santosh Shilimkar
2013-01-31 17:16 ` Nicolas Pitre
2013-02-01 5:10 ` Santosh Shilimkar [this message]
2013-02-01 17:26 ` Nicolas Pitre
2013-01-29 7:50 ` [PATCH v3 04/15] ARM: mcpm: Add baremetal voting mutexes Nicolas Pitre
2013-02-01 5:29 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 05/15] ARM: mcpm_head.S: vlock-based first man election Nicolas Pitre
2013-02-01 5:34 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 06/15] ARM: mcpm: generic SMP secondary bringup and hotplug support Nicolas Pitre
2013-01-29 20:38 ` Rob Herring
2013-02-01 5:38 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 07/15] ARM: vexpress: Select the correct SMP operations at run-time Nicolas Pitre
2013-01-29 15:43 ` Jon Medhurst (Tixy)
2013-01-29 19:26 ` Nicolas Pitre
2013-02-01 5:41 ` Santosh Shilimkar
2013-02-01 17:28 ` Nicolas Pitre
2013-01-29 7:51 ` [PATCH v3 08/15] ARM: introduce common set_auxcr/get_auxcr functions Nicolas Pitre
2013-02-01 5:44 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 09/15] ARM: vexpress: introduce DCSCB support Nicolas Pitre
2013-02-01 5:50 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 10/15] ARM: vexpress/dcscb: add CPU use counts to the power up/down API implementation Nicolas Pitre
2013-02-01 5:53 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 11/15] ARM: vexpress/dcscb: do not hardcode number of CPUs per cluster Nicolas Pitre
2013-02-01 5:57 ` Santosh Shilimkar
2013-02-01 17:24 ` Nicolas Pitre
2013-02-02 6:54 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 12/15] drivers/bus: add ARM CCI support Nicolas Pitre
2013-02-01 6:01 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 13/15] ARM: CCI: ensure powerdown-time data is flushed from cache Nicolas Pitre
2013-02-01 6:13 ` Santosh Shilimkar
2013-02-02 22:23 ` Nicolas Pitre
2013-02-03 10:07 ` Santosh Shilimkar
2013-02-03 18:29 ` Nicolas Pitre
2013-02-04 5:25 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 14/15] ARM: vexpress/dcscb: handle platform coherency exit/setup and CCI Nicolas Pitre
2013-01-29 10:46 ` Lorenzo Pieralisi
2013-01-29 18:42 ` Nicolas Pitre
2013-01-30 17:27 ` Lorenzo Pieralisi
2013-02-01 6:15 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 15/15] ARM: vexpress/dcscb: probe via device tree Nicolas Pitre
2013-01-29 21:01 ` Rob Herring
2013-01-29 21:41 ` Nicolas Pitre
2013-01-30 12:22 ` Achin Gupta
2013-01-30 17:43 ` Nicolas Pitre
2013-01-31 10:54 ` Dave Martin
2013-02-04 4:39 ` Nicolas Pitre
2013-02-04 14:24 ` [PATCH v3 00/15] multi-cluster power management Will Deacon
2013-02-04 20:59 ` Nicolas Pitre
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