From: santosh.shilimkar@ti•com (Santosh Shilimkar)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v3 09/15] ARM: vexpress: introduce DCSCB support
Date: Fri, 1 Feb 2013 11:20:04 +0530 [thread overview]
Message-ID: <510B578C.4090102@ti.com> (raw)
In-Reply-To: <1359445870-18925-10-git-send-email-nicolas.pitre@linaro.org>
On Tuesday 29 January 2013 01:21 PM, Nicolas Pitre wrote:
> This adds basic CPU and cluster reset controls on RTSM for the
> A15x4-A7x4 model configuration using the Dual Cluster System
> Configuration Block (DCSCB).
>
> The cache coherency interconnect (CCI) is not handled yet.
>
> Signed-off-by: Nicolas Pitre <nico@linaro•org>
> ---
> arch/arm/mach-vexpress/Kconfig | 8 ++
> arch/arm/mach-vexpress/Makefile | 1 +
> arch/arm/mach-vexpress/dcscb.c | 159 ++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 168 insertions(+)
> create mode 100644 arch/arm/mach-vexpress/dcscb.c
>
> diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
> index 52d315b792..f3f92b120a 100644
> --- a/arch/arm/mach-vexpress/Kconfig
> +++ b/arch/arm/mach-vexpress/Kconfig
> @@ -52,4 +52,12 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
> config ARCH_VEXPRESS_CA9X4
> bool "Versatile Express Cortex-A9x4 tile"
>
> +config ARCH_VEXPRESS_DCSCB
> + bool "Dual Cluster System Control Block (DCSCB) support"
> + depends on CLUSTER_PM
> + help
> + Support for the Dual Cluster System Configuration Block (DCSCB).
> + This is needed to provide CPU and cluster power management
> + on RTSM.
> +
> endmenu
> diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
> index 80b64971fb..2253644054 100644
> --- a/arch/arm/mach-vexpress/Makefile
> +++ b/arch/arm/mach-vexpress/Makefile
> @@ -6,5 +6,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
>
> obj-y := v2m.o reset.o
> obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o
> +obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o
> obj-$(CONFIG_SMP) += platsmp.o
> obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
> diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
> new file mode 100644
> index 0000000000..677ced9efc
> --- /dev/null
> +++ b/arch/arm/mach-vexpress/dcscb.c
> @@ -0,0 +1,159 @@
> +/*
> + * arch/arm/mach-vexpress/dcscb.c - Dual Cluster System Control Block
> + *
> + * Created by: Nicolas Pitre, May 2012
> + * Copyright: (C) 2012-2013 Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/io.h>
> +#include <linux/spinlock.h>
> +#include <linux/errno.h>
> +#include <linux/vexpress.h>
> +
> +#include <asm/mcpm_entry.h>
> +#include <asm/proc-fns.h>
> +#include <asm/cacheflush.h>
> +#include <asm/cputype.h>
> +#include <asm/cp15.h>
> +
> +
> +#define DCSCB_PHYS_BASE 0x60000000
> +
> +#define RST_HOLD0 0x0
> +#define RST_HOLD1 0x4
> +#define SYS_SWRESET 0x8
> +#define RST_STAT0 0xc
> +#define RST_STAT1 0x10
> +#define EAG_CFG_R 0x20
> +#define EAG_CFG_W 0x24
> +#define KFC_CFG_R 0x28
> +#define KFC_CFG_W 0x2c
> +#define DCS_CFG_R 0x30
> +
> +/*
> + * We can't use regular spinlocks. In the switcher case, it is possible
> + * for an outbound CPU to call power_down() after its inbound counterpart
> + * is already live using the same logical CPU number which trips lockdep
> + * debugging.
> + */
> +static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED;
> +
> +static void __iomem *dcscb_base;
> +
> +static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
> +{
> + unsigned int rst_hold, cpumask = (1 << cpu);
> +
> + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> + if (cpu >= 4 || cluster >= 2)
Is this a CCI limitation ?
> + return -EINVAL;
> +
> + /*
> + * Since this is called with IRQs enabled, and no arch_spin_lock_irq
> + * variant exists, we need to disable IRQs manually here.
> + */
> + local_irq_disable();
> + arch_spin_lock(&dcscb_lock);
> +
> + rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
> + if (rst_hold & (1 << 8)) {
> + /* remove cluster reset and add individual CPU's reset */
> + rst_hold &= ~(1 << 8);
> + rst_hold |= 0xf;
> + }
> + rst_hold &= ~(cpumask | (cpumask << 4));
> + writel(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
> +
> + arch_spin_unlock(&dcscb_lock);
> + local_irq_enable();
> +
> + return 0;
> +}
> +
> +static void dcscb_power_down(void)
> +{
> + unsigned int mpidr, cpu, cluster, rst_hold, cpumask, last_man;
> +
> + mpidr = read_cpuid_mpidr();
> + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
> + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
> + cpumask = (1 << cpu);
> +
> + pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
> + BUG_ON(cpu >= 4 || cluster >= 2);
> +
> + arch_spin_lock(&dcscb_lock);
> + rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
> + rst_hold |= cpumask;
> + if (((rst_hold | (rst_hold >> 4)) & 0xf) == 0xf)
> + rst_hold |= (1 << 8);
> + writel(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
> + arch_spin_unlock(&dcscb_lock);
> + last_man = (rst_hold & (1 << 8));
> +
> + /*
> + * Now let's clean our L1 cache and shut ourself down.
> + * If we're the last CPU in this cluster then clean L2 too.
> + */
> +
How about merging these two comments ?
> + /*
> + * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
> + * a preliminary flush here for those CPUs. At least, that's
> + * the theory -- without the extra flush, Linux explodes on
> + * RTSM (maybe not needed anymore, to be investigated)..
> + */
> + flush_cache_louis();
> + cpu_proc_fin();
Lorenzo already noticed the I cache getting disable here.
That should be fixed. Rest of the patch looks fine.
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti•com>
next prev parent reply other threads:[~2013-02-01 5:50 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-29 7:50 [PATCH v3 00/15] multi-cluster power management Nicolas Pitre
2013-01-29 7:50 ` [PATCH v3 01/15] ARM: multi-cluster PM: secondary kernel entry code Nicolas Pitre
2013-01-31 15:45 ` Santosh Shilimkar
2013-01-29 7:50 ` [PATCH v3 02/15] ARM: mcpm: introduce the CPU/cluster power API Nicolas Pitre
2013-01-31 15:55 ` Santosh Shilimkar
2013-01-29 7:50 ` [PATCH v3 03/15] ARM: mcpm: introduce helpers for platform coherency exit/setup Nicolas Pitre
2013-01-31 16:08 ` Santosh Shilimkar
2013-01-31 17:16 ` Nicolas Pitre
2013-02-01 5:10 ` Santosh Shilimkar
2013-02-01 17:26 ` Nicolas Pitre
2013-01-29 7:50 ` [PATCH v3 04/15] ARM: mcpm: Add baremetal voting mutexes Nicolas Pitre
2013-02-01 5:29 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 05/15] ARM: mcpm_head.S: vlock-based first man election Nicolas Pitre
2013-02-01 5:34 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 06/15] ARM: mcpm: generic SMP secondary bringup and hotplug support Nicolas Pitre
2013-01-29 20:38 ` Rob Herring
2013-02-01 5:38 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 07/15] ARM: vexpress: Select the correct SMP operations at run-time Nicolas Pitre
2013-01-29 15:43 ` Jon Medhurst (Tixy)
2013-01-29 19:26 ` Nicolas Pitre
2013-02-01 5:41 ` Santosh Shilimkar
2013-02-01 17:28 ` Nicolas Pitre
2013-01-29 7:51 ` [PATCH v3 08/15] ARM: introduce common set_auxcr/get_auxcr functions Nicolas Pitre
2013-02-01 5:44 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 09/15] ARM: vexpress: introduce DCSCB support Nicolas Pitre
2013-02-01 5:50 ` Santosh Shilimkar [this message]
2013-01-29 7:51 ` [PATCH v3 10/15] ARM: vexpress/dcscb: add CPU use counts to the power up/down API implementation Nicolas Pitre
2013-02-01 5:53 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 11/15] ARM: vexpress/dcscb: do not hardcode number of CPUs per cluster Nicolas Pitre
2013-02-01 5:57 ` Santosh Shilimkar
2013-02-01 17:24 ` Nicolas Pitre
2013-02-02 6:54 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 12/15] drivers/bus: add ARM CCI support Nicolas Pitre
2013-02-01 6:01 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 13/15] ARM: CCI: ensure powerdown-time data is flushed from cache Nicolas Pitre
2013-02-01 6:13 ` Santosh Shilimkar
2013-02-02 22:23 ` Nicolas Pitre
2013-02-03 10:07 ` Santosh Shilimkar
2013-02-03 18:29 ` Nicolas Pitre
2013-02-04 5:25 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 14/15] ARM: vexpress/dcscb: handle platform coherency exit/setup and CCI Nicolas Pitre
2013-01-29 10:46 ` Lorenzo Pieralisi
2013-01-29 18:42 ` Nicolas Pitre
2013-01-30 17:27 ` Lorenzo Pieralisi
2013-02-01 6:15 ` Santosh Shilimkar
2013-01-29 7:51 ` [PATCH v3 15/15] ARM: vexpress/dcscb: probe via device tree Nicolas Pitre
2013-01-29 21:01 ` Rob Herring
2013-01-29 21:41 ` Nicolas Pitre
2013-01-30 12:22 ` Achin Gupta
2013-01-30 17:43 ` Nicolas Pitre
2013-01-31 10:54 ` Dave Martin
2013-02-04 4:39 ` Nicolas Pitre
2013-02-04 14:24 ` [PATCH v3 00/15] multi-cluster power management Will Deacon
2013-02-04 20:59 ` Nicolas Pitre
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=510B578C.4090102@ti.com \
--to=santosh.shilimkar@ti$(echo .)com \
--cc=linux-arm-kernel@lists$(echo .)infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox