From: pgaikwad@nvidia•com (Prashant Gaikwad)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v5 02/10] clk: tegra: Add TEGRA_PLL_BYPASS flag
Date: Mon, 4 Feb 2013 11:43:28 +0530 [thread overview]
Message-ID: <510F5188.3010806@nvidia.com> (raw)
In-Reply-To: <1359713962-16822-3-git-send-email-pdeschrijver@nvidia.com>
On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
> Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
> this bit when available.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia•com>
> ---
Looks good to me.
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia•com>
> drivers/clk/tegra/clk-pll.c | 15 ++++++++++-----
> drivers/clk/tegra/clk.h | 8 +++++---
> 2 files changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
> index 912c977..3c3a25e 100644
> --- a/drivers/clk/tegra/clk-pll.c
> +++ b/drivers/clk/tegra/clk-pll.c
> @@ -166,7 +166,8 @@ static void _clk_pll_enable(struct clk_hw *hw)
> clk_pll_enable_lock(pll);
>
> val = pll_readl_base(pll);
> - val &= ~PLL_BASE_BYPASS;
> + if (pll->flags & TEGRA_PLL_BYPASS)
> + val &= ~PLL_BASE_BYPASS;
> val |= PLL_BASE_ENABLE;
> pll_writel_base(val, pll);
>
> @@ -183,7 +184,9 @@ static void _clk_pll_disable(struct clk_hw *hw)
> u32 val;
>
> val = pll_readl_base(pll);
> - val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
> + if (pll->flags & TEGRA_PLL_BYPASS)
> + val &= ~PLL_BASE_BYPASS;
> + val &= ~PLL_BASE_ENABLE;
> pll_writel_base(val, pll);
>
> if (pll->flags & TEGRA_PLLM) {
> @@ -454,7 +457,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
>
> val = pll_readl_base(pll);
>
> - if (val & PLL_BASE_BYPASS)
> + if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
> return parent_rate;
>
> if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) {
> @@ -660,9 +663,10 @@ static struct clk *_tegra_clk_register_pll(const char *name,
> struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
> void __iomem *clk_base, void __iomem *pmc,
> unsigned long flags, unsigned long fixed_rate,
> - struct tegra_clk_pll_params *pll_params, u8 pll_flags,
> + struct tegra_clk_pll_params *pll_params, u32 pll_flags,
> struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
> {
> + pll_flags |= TEGRA_PLL_BYPASS;
> return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
> flags, fixed_rate, pll_params, pll_flags, freq_table,
> lock, &tegra_clk_pll_ops);
> @@ -671,9 +675,10 @@ struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
> struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
> void __iomem *clk_base, void __iomem *pmc,
> unsigned long flags, unsigned long fixed_rate,
> - struct tegra_clk_pll_params *pll_params, u8 pll_flags,
> + struct tegra_clk_pll_params *pll_params, u32 pll_flags,
> struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
> {
> + pll_flags |= TEGRA_PLL_BYPASS;
> return _tegra_clk_register_pll(name, parent_name, clk_base, pmc,
> flags, fixed_rate, pll_params, pll_flags, freq_table,
> lock, &tegra_clk_plle_ops);
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index a09d7dc..3cff1df 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -182,12 +182,13 @@ struct tegra_clk_pll_params {
> * TEGRA_PLL_FIXED - We are not supposed to change output frequency
> * of some plls.
> * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
> + * TEGRA_PLL_BYPASS - PLL has bypass bit
> */
> struct tegra_clk_pll {
> struct clk_hw hw;
> void __iomem *clk_base;
> void __iomem *pmc;
> - u8 flags;
> + u32 flags;
> unsigned long fixed_rate;
> spinlock_t *lock;
> u8 divn_shift;
> @@ -210,18 +211,19 @@ struct tegra_clk_pll {
> #define TEGRA_PLLM BIT(5)
> #define TEGRA_PLL_FIXED BIT(6)
> #define TEGRA_PLLE_CONFIGURE BIT(7)
> +#define TEGRA_PLL_BYPASS BIT(8)
>
> extern const struct clk_ops tegra_clk_pll_ops;
> extern const struct clk_ops tegra_clk_plle_ops;
> struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
> void __iomem *clk_base, void __iomem *pmc,
> unsigned long flags, unsigned long fixed_rate,
> - struct tegra_clk_pll_params *pll_params, u8 pll_flags,
> + struct tegra_clk_pll_params *pll_params, u32 pll_flags,
> struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
> struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
> void __iomem *clk_base, void __iomem *pmc,
> unsigned long flags, unsigned long fixed_rate,
> - struct tegra_clk_pll_params *pll_params, u8 pll_flags,
> + struct tegra_clk_pll_params *pll_params, u32 pll_flags,
> struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
>
> /**
next prev parent reply other threads:[~2013-02-04 6:13 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-01 10:18 [PATCH v5 00/10] Tegra114 clockframework Peter De Schrijver
2013-02-01 10:18 ` [PATCH v5 01/10] clk: tegra: Refactor PLL programming code Peter De Schrijver
2013-02-04 6:06 ` Prashant Gaikwad
2013-02-04 14:32 ` Peter De Schrijver
2013-02-05 5:42 ` Prashant Gaikwad
2013-02-05 13:23 ` Peter De Schrijver
2013-02-06 12:32 ` Peter De Schrijver
2013-02-04 21:57 ` Stephen Warren
2013-02-01 10:18 ` [PATCH v5 02/10] clk: tegra: Add TEGRA_PLL_BYPASS flag Peter De Schrijver
2013-02-04 6:13 ` Prashant Gaikwad [this message]
2013-02-01 10:18 ` [PATCH v5 03/10] clk: tegra: Add PLL post divider table Peter De Schrijver
2013-02-04 6:28 ` Prashant Gaikwad
2013-02-01 10:18 ` [PATCH v5 04/10] clk: tegra: Add new fields and PLL types for Tegra114 Peter De Schrijver
2013-02-01 19:40 ` Rhyland Klein
2013-02-04 6:35 ` Prashant Gaikwad
2013-02-04 10:37 ` Peter De Schrijver
2013-02-01 10:18 ` [PATCH v5 05/10] clk: tegra: Add flags to tegra_clk_periph() Peter De Schrijver
2013-02-04 6:33 ` Prashant Gaikwad
2013-02-01 10:18 ` [PATCH v5 06/10] clk: tegra: Workaround for Tegra114 MSENC problem Peter De Schrijver
2013-02-04 6:39 ` Prashant Gaikwad
2013-02-01 10:18 ` [PATCH v5 07/10] ARM: tegra: Define Tegra114 CAR binding Peter De Schrijver
2013-02-04 21:16 ` Stephen Warren
2013-02-01 10:18 ` [PATCH v5 08/10] ARM: dt: Add references to tegra_car clocks Peter De Schrijver
2013-02-04 6:45 ` Prashant Gaikwad
2013-02-01 10:18 ` [PATCH v5 09/10] clk: tegra: Implement clocks for Tegra114 Peter De Schrijver
2013-02-04 7:08 ` Prashant Gaikwad
2013-02-04 10:45 ` Peter De Schrijver
2013-02-04 14:07 ` Peter De Schrijver
2013-02-04 21:01 ` Stephen Warren
2013-02-07 16:18 ` Peter De Schrijver
2013-02-04 14:34 ` Peter De Schrijver
2013-02-05 5:36 ` Prashant Gaikwad
2013-02-01 10:18 ` [PATCH v5 10/10] clk: tegra: devicetree match for nvidia, tegra114-car Peter De Schrijver
2013-02-04 7:10 ` Prashant Gaikwad
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