From: pgaikwad@nvidia•com (Prashant Gaikwad)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v5 01/10] clk: tegra: Refactor PLL programming code
Date: Tue, 5 Feb 2013 11:12:11 +0530 [thread overview]
Message-ID: <51109BB3.8000706@nvidia.com> (raw)
In-Reply-To: <20130204143233.GV2364@tbergstrom-lnx.Nvidia.com>
On Monday 04 February 2013 08:02 PM, Peter De Schrijver wrote:
> On Mon, Feb 04, 2013 at 07:06:47AM +0100, Prashant Gaikwad wrote:
>> On Friday 01 February 2013 03:48 PM, Peter De Schrijver wrote:
> ...
>
>>> -static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll,
>>> - void __iomem *lock_addr, u32 lock_bit_idx)
>>> +static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
>>> {
>>> int i;
>>> - u32 val;
>>> + u32 val, lock_bit;
>>> + void __iomem *lock_addr;
>>>
>>> if (!(pll->flags & TEGRA_PLL_USE_LOCK)) {
>>> udelay(pll->params->lock_delay);
>>> return 0;
>>> }
>>>
>>> + lock_addr = pll->clk_base + pll->params->base_reg;
>> This will not work for PLLE. Lock bit for PLLE is in misc register.
>>
>>> + lock_bit = BIT(pll->params->lock_bit_idx);
>>> +
>>> for (i = 0; i < pll->params->lock_delay; i++) {
>>> val = readl_relaxed(lock_addr);
>>> - if (val & BIT(lock_bit_idx)) {
>>> + if (val & lock_bit) {
>> Need to change the lock bit idx parameter for Tegra20 and Tegra30 PLLs
>> else this patch will break those.
>>
> Looking at commit 37c26a906527b8a6a252614ca83d21ad318c4e84 and commit
> b08e8c0ecc42afa3a2e1019851af741980dd5a6b, these fields seem correctly
> initialized for both Tegra20 and Tegra30? Or am I missing something?
Ohh, I missed to read
lock_bit = BIT(pll->params->lock_bit_idx);
Am I missing something about PLLE lock_addr also?
> Thanks,
>
> Peter.
next prev parent reply other threads:[~2013-02-05 5:42 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-01 10:18 [PATCH v5 00/10] Tegra114 clockframework Peter De Schrijver
2013-02-01 10:18 ` [PATCH v5 01/10] clk: tegra: Refactor PLL programming code Peter De Schrijver
2013-02-04 6:06 ` Prashant Gaikwad
2013-02-04 14:32 ` Peter De Schrijver
2013-02-05 5:42 ` Prashant Gaikwad [this message]
2013-02-05 13:23 ` Peter De Schrijver
2013-02-06 12:32 ` Peter De Schrijver
2013-02-04 21:57 ` Stephen Warren
2013-02-01 10:18 ` [PATCH v5 02/10] clk: tegra: Add TEGRA_PLL_BYPASS flag Peter De Schrijver
2013-02-04 6:13 ` Prashant Gaikwad
2013-02-01 10:18 ` [PATCH v5 03/10] clk: tegra: Add PLL post divider table Peter De Schrijver
2013-02-04 6:28 ` Prashant Gaikwad
2013-02-01 10:18 ` [PATCH v5 04/10] clk: tegra: Add new fields and PLL types for Tegra114 Peter De Schrijver
2013-02-01 19:40 ` Rhyland Klein
2013-02-04 6:35 ` Prashant Gaikwad
2013-02-04 10:37 ` Peter De Schrijver
2013-02-01 10:18 ` [PATCH v5 05/10] clk: tegra: Add flags to tegra_clk_periph() Peter De Schrijver
2013-02-04 6:33 ` Prashant Gaikwad
2013-02-01 10:18 ` [PATCH v5 06/10] clk: tegra: Workaround for Tegra114 MSENC problem Peter De Schrijver
2013-02-04 6:39 ` Prashant Gaikwad
2013-02-01 10:18 ` [PATCH v5 07/10] ARM: tegra: Define Tegra114 CAR binding Peter De Schrijver
2013-02-04 21:16 ` Stephen Warren
2013-02-01 10:18 ` [PATCH v5 08/10] ARM: dt: Add references to tegra_car clocks Peter De Schrijver
2013-02-04 6:45 ` Prashant Gaikwad
2013-02-01 10:18 ` [PATCH v5 09/10] clk: tegra: Implement clocks for Tegra114 Peter De Schrijver
2013-02-04 7:08 ` Prashant Gaikwad
2013-02-04 10:45 ` Peter De Schrijver
2013-02-04 14:07 ` Peter De Schrijver
2013-02-04 21:01 ` Stephen Warren
2013-02-07 16:18 ` Peter De Schrijver
2013-02-04 14:34 ` Peter De Schrijver
2013-02-05 5:36 ` Prashant Gaikwad
2013-02-01 10:18 ` [PATCH v5 10/10] clk: tegra: devicetree match for nvidia, tegra114-car Peter De Schrijver
2013-02-04 7:10 ` Prashant Gaikwad
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