From: swarren@wwwdotorg•org (Stephen Warren)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 3/5] clk: tegra: Fix vde/2d/3d clock src offset
Date: Wed, 07 Aug 2013 11:00:08 -0600 [thread overview]
Message-ID: <52027D18.5040106@wwwdotorg.org> (raw)
In-Reply-To: <1375874709-10438-3-git-send-email-markz@nvidia.com>
On 08/07/2013 05:25 AM, Mark Zhang wrote:
> In Tegra114, vde/gr_2d/gr_3d have 3 bits for clock source selection.
> So change the clock init macro for these clocks from
> "TEGRA_INIT_DATA_INT" to "TEGRA_INIT_DATA_INT8".
>
> Besides, no one uses "TEGRA_INIT_DATA_INT" after this change, so
> remove this macro.
Patches 3-5 look fine as far as I'm concerned, although I'd like Peter
or Prashant to ack them too.
Patches 3-5,
Acked-by: Stephen Warren <swarren@nvidia•com>
next prev parent reply other threads:[~2013-08-07 17:00 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-07 11:25 [PATCH 1/5] clk: tegra: Correct sbc mux width & parent Mark Zhang
2013-08-07 11:25 ` [PATCH 2/5] clk: tegra: Add reset only clock node flag and COP Mark Zhang
2013-08-07 16:58 ` Stephen Warren
2013-08-08 5:50 ` Mark Zhang
2013-08-19 14:53 ` Peter De Schrijver
2013-08-19 16:25 ` Stephen Warren
2013-08-07 11:25 ` [PATCH 3/5] clk: tegra: Fix vde/2d/3d clock src offset Mark Zhang
2013-08-07 17:00 ` Stephen Warren [this message]
2013-08-20 8:47 ` Peter De Schrijver
2013-08-07 11:25 ` [PATCH 4/5] clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2 Mark Zhang
2013-08-20 8:47 ` Peter De Schrijver
2013-08-07 11:25 ` [PATCH 5/5] clk: tegra: Set the clk parent of host1x to pll_p Mark Zhang
2013-08-07 16:56 ` [PATCH 1/5] clk: tegra: Correct sbc mux width & parent Stephen Warren
2013-08-08 1:26 ` Mark Zhang
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