From: gregory.clement@free-electrons•com (Gregory CLEMENT)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v2 00/12] CPU idle for Armada XP
Date: Fri, 13 Sep 2013 13:17:17 +0200 [thread overview]
Message-ID: <5232F43D.4040404@free-electrons.com> (raw)
In-Reply-To: <20130913110043.GJ19363@lunn.ch>
On 13/09/2013 13:00, Andrew Lunn wrote:
>
> On Fri, Sep 13, 2013 at 12:06:29PM +0200, Gregory CLEMENT wrote:
>> Hello,
>>
>> This patch set adds the CPU idle support for Armada XP and prepares
>> the support for Armada 370. This was based on the work of Nadav
>> Haklai.
>
> Hi Gregory.
>
> Kirkwood has the ability to put the DDR into self refresh mode, which
> is used as part of the second level idle mode. Does 370/XP have this?
Indeed there is a self refresh bit on a DDR related register. I thought
this kind of feature is more likely used for suspend to ram.
We plan to also submit the suspend to ram but not immediately.
>
> For XP, with it being SMP, it would be a bit more complex, since you
> would not want to use it unless all CPUs were idle.
I wonder how the others SMP ARM SoCs deal with it, I hope this time
there will be a framework available and we won't have to create it! ;)
>
> Thanks
> Andrew
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
next prev parent reply other threads:[~2013-09-13 11:17 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-13 10:06 [PATCH v2 00/12] CPU idle for Armada XP Gregory CLEMENT
2013-09-13 10:06 ` [PATCH v2 01/12] ARM: PJ4B: Add cpu_suspend/cpu_resume hooks for PJ4B Gregory CLEMENT
2013-09-13 10:06 ` [PATCH v2 02/12] ARM: mvebu: ll_set_cpu_coherent no more uses the coherency address as parameter Gregory CLEMENT
2013-09-13 10:06 ` [PATCH v2 03/12] ARM: mvebu: ll_set_cpu_coherent always uses the current CPU Gregory CLEMENT
2013-09-13 10:06 ` [PATCH v2 04/12] ARM: mvebu: Remove the unused argument of set_cpu_coherent() Gregory CLEMENT
2013-09-13 10:06 ` [PATCH v2 05/12] ARM: mvebu: Make ll_set_cpu_coherent() more configurable Gregory CLEMENT
2013-09-13 10:06 ` [PATCH v2 06/12] ARM: mvebu: Low level functions to disable cache snooping Gregory CLEMENT
2013-09-13 10:06 ` [PATCH v2 07/12] ARM: mvebu: Add a new set of registers for pmsu Gregory CLEMENT
2013-09-13 10:06 ` [PATCH v2 08/12] ARM: mvebu: Allow to power down L2 cache controller in idle mode Gregory CLEMENT
2013-09-13 10:06 ` [PATCH v2 09/12] ARM: mvebu: Add the PMSU related part of the cpu idle functions Gregory CLEMENT
2013-09-13 10:06 ` [PATCH v2 10/12] ARM: mvebu: Set the start address of a CPU in a separate function Gregory CLEMENT
2013-09-13 10:06 ` [PATCH v2 11/12] cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoC Gregory CLEMENT
2013-09-13 15:36 ` Daniel Lezcano
2013-09-15 14:34 ` Gregory CLEMENT
2013-09-15 17:31 ` Daniel Lezcano
2013-10-14 14:01 ` Gregory CLEMENT
2013-09-13 16:16 ` Lorenzo Pieralisi
2013-10-14 14:14 ` Gregory CLEMENT
2013-10-14 15:06 ` Lorenzo Pieralisi
2013-09-13 10:06 ` [PATCH v2 12/12] ARM: dts: mvebu: Add a new set of registers to the PMSU node Gregory CLEMENT
2013-09-13 11:00 ` [PATCH v2 00/12] CPU idle for Armada XP Andrew Lunn
2013-09-13 11:17 ` Gregory CLEMENT [this message]
2013-09-13 11:38 ` Andrew Lunn
2013-09-13 14:48 ` Kevin Hilman
2013-09-13 15:19 ` Daniel Lezcano
2013-10-02 17:39 ` Jason Cooper
2013-10-02 17:44 ` Gregory CLEMENT
2013-10-02 17:58 ` Jason Cooper
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