From: kishon@ti•com (Kishon Vijay Abraham I)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for configuring the iATU
Date: Tue, 13 May 2014 18:56:23 +0530 [thread overview]
Message-ID: <53721D7F.9070200@ti.com> (raw)
In-Reply-To: <10531498.kYV5eO1J1m@wuerfel>
Hi Arnd,
On Tuesday 13 May 2014 06:17 PM, Arnd Bergmann wrote:
> On Tuesday 13 May 2014 18:01:59 Kishon Vijay Abraham I wrote:
>> On Thursday 08 May 2014 02:48 PM, Arnd Bergmann wrote:
>>> On Thursday 08 May 2014 18:05:11 Jingoo Han wrote:
>>>> On Tuesday, May 06, 2014 10:59 PM, Arnd Bergmann wrote:
>>>>> On Tuesday 06 May 2014 19:03:52 Kishon Vijay Abraham I wrote:
>>>>>> In DRA7, the cpu sees 32bit address, but the pcie controller can see only 28bit
>>>>>> address. So whenever the cpu issues a read/write request, the 4 most
>>>>>> significant bits are used by L3 to determine the target controller.
>>>>>> For example, the cpu reserves 0x2000_0000 - 0x2FFF_FFFF for PCIe controller but
>>>>>> the PCIe controller will see only (0x000_0000 - 0xFFF_FFF). So for programming
>>>>>> the outbound translation window the *base* should be programmed as 0x000_0000.
>>>>>> Whenever we try to write to say 0x2000_0000, it will be translated to whatever
>>>>>> we have programmed in the translation window with base as 0x000_0000.
>>>>>>
>>>>>> Cc: Bjorn Helgaas <bhelgaas@google•com>
>>>>>> Cc: Marek Vasut <marex@denx•de>
>>>>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti•com>
>>>>>> Acked-by: Jingoo Han <jg1.han@samsung•com>
>>>>>> Acked-by: Mohit Kumar <mohit.kumar@st•com>
>>>>>
>>>>> Sorry, but NAK.
>>>>>
>>>>> We have a standard 'dma-ranges' property to handle this, so use it.
>>>>>
>>>>> See the x-gene PCIe driver patches for an example. Please also talk
>>>>> to Santosh about it, as he is implementing generic support for
>>>>> parsing dma-ranges in platform devices at the moment.
>>>>
>>>> Hi Arnd,
>>>>
>>>> Do you mean the following patch?
>>>> http://www.spinics.net/lists/kernel/msg1737725.html
>>>>
>>>
>>> That is the patch Santosh did for platform devices, which is related but not
>>> what I meant here. For the PCI inbound window setup, please have a look
>>> at https://lkml.org/lkml/2014/3/19/607
>>
>> Do you think it can be used for *outbound* window setup too? The problem is the
>> *ranges* property defines both the pci address and cpu address which should
>> have been enough to program the ob translation window, but the hw is designed
>> so that the controller sees only the 28 bits. (The most significant 4 bits is
>> for the l3 to address the controller).
>
> I'm not following what the problem is. You should always be able to describe
> in the inbound window (that is from the CPU perspective) using dma-ranges
> and the outbound window using ranges.
>
> If you have a case where the outbound translation is a 256MB (i.e. 28bit)
> section of the CPU address space, that could be represented as
>
> ranges = <0x82000000 0 0 0xb0000000 0 0x10000000>;
>
> or
>
> ranges = <0x82000000 0 0xb0000000 0xb0000000 0 0x10000000>;
>
> depending on whether you want the BARs to be programmed using a low
> address 0x0-0x0fffffff or an address matching the window
> 0xb0000000-0xbfffffff.
The problem is, for configuring the window starting at 0xb0000000, the ATU
should be programmed 0x0000000 (the cpu address for it will be 0xb0000000 though).
Thanks
Kishon
next prev parent reply other threads:[~2014-05-13 13:26 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-06 13:33 [PATCH 00/17] PCIe support for DRA7xx Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 01/17] phy: phy-omap-pipe3: Add support for PCIe PHY Kishon Vijay Abraham I
2014-05-14 12:57 ` Roger Quadros
2014-05-06 13:33 ` [PATCH 02/17] phy: omap-control: add external clock " Kishon Vijay Abraham I
2014-05-14 13:02 ` Roger Quadros
2014-05-06 13:33 ` [PATCH 03/17] phy: ti-pipe3: " Kishon Vijay Abraham I
2014-05-14 13:16 ` Roger Quadros
2014-05-14 15:19 ` Kishon Vijay Abraham I
2014-05-14 15:34 ` Nishanth Menon
2014-05-15 9:15 ` Kishon Vijay Abraham I
2014-05-15 9:25 ` Roger Quadros
2014-05-15 11:46 ` Nishanth Menon
2014-05-15 11:59 ` Kishon Vijay Abraham I
2014-05-15 12:12 ` Nishanth Menon
2014-05-15 12:18 ` Kishon Vijay Abraham I
2014-05-15 12:33 ` Nishanth Menon
2014-05-15 12:42 ` Kishon Vijay Abraham I
2014-05-27 6:11 ` Kishon Vijay Abraham I
2014-05-28 1:54 ` Mike Turquette
2014-05-28 15:52 ` Nishanth Menon
2014-05-06 13:33 ` [PATCH 04/17] phy: pipe3: insert delay to enumerate in GEN2 mode Kishon Vijay Abraham I
2014-05-14 13:20 ` Roger Quadros
2014-05-06 13:33 ` [PATCH 05/17] pci: host: pcie-dra7xx: add support for pcie-dra7xx controller Kishon Vijay Abraham I
2014-05-06 13:44 ` Marek Vasut
2014-05-07 8:21 ` Kishon Vijay Abraham I
2014-05-09 9:43 ` Pavel Machek
2014-05-06 13:54 ` Arnd Bergmann
2014-05-07 8:44 ` Kishon Vijay Abraham I
2014-05-07 9:30 ` Arnd Bergmann
2014-05-09 11:29 ` Kishon Vijay Abraham I
2014-05-06 16:35 ` Jason Gunthorpe
2014-05-07 9:22 ` Kishon Vijay Abraham I
2014-05-07 9:25 ` Arnd Bergmann
2014-05-08 8:56 ` Jingoo Han
2014-05-08 9:16 ` Arnd Bergmann
2014-05-06 13:33 ` [PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for configuring the iATU Kishon Vijay Abraham I
2014-05-06 13:59 ` Arnd Bergmann
2014-05-08 9:05 ` Jingoo Han
2014-05-08 9:18 ` Arnd Bergmann
2014-05-09 11:50 ` Kishon Vijay Abraham I
2014-05-12 1:44 ` Jingoo Han
2014-05-13 12:31 ` Kishon Vijay Abraham I
2014-05-13 12:47 ` Arnd Bergmann
2014-05-13 13:26 ` Kishon Vijay Abraham I [this message]
2014-05-13 13:27 ` Arnd Bergmann
2014-05-13 13:34 ` Arnd Bergmann
2014-05-14 5:44 ` Kishon Vijay Abraham I
2014-05-14 12:45 ` Arnd Bergmann
2014-05-14 15:04 ` Kishon Vijay Abraham I
2014-05-16 9:00 ` Kishon Vijay Abraham I
2014-05-19 12:45 ` Arnd Bergmann
2014-05-06 13:33 ` [PATCH 07/17] ARM: dts: DRA7: Add divider table to optfclk_pciephy_div clock Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 08/17] ARM: dts: DRA7: Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 09/17] arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 10/17] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 11/17] ARM: dts: dra7xx-clocks: Add missing 32khz clocks used for PHY Kishon Vijay Abraham I
2014-05-14 13:23 ` Roger Quadros
2014-05-14 15:19 ` Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 12/17] ARM: dts: dra7: Add dt data for PCIe PHY control module Kishon Vijay Abraham I
2014-05-06 13:33 ` [PATCH 13/17] ARM: dts: dra7: Add dt data for PCIe PHY Kishon Vijay Abraham I
2014-05-06 13:34 ` [PATCH 14/17] ARM: dts: dra7: Add dt data for PCIe controller Kishon Vijay Abraham I
2014-05-06 13:34 ` [PATCH 15/17] ARM: OMAP: Enable PCI for DRA7 Kishon Vijay Abraham I
2014-05-06 13:34 ` [TEMP PATCH 16/17] pci: host: pcie-dra7xx: use reset framework APIs to reset PCIe Kishon Vijay Abraham I
2014-05-06 13:41 ` Dan Murphy
2014-05-06 13:34 ` [TEMP PATCH 17/17] ARM: dts: dra7: Add *resets* property for PCIe dt node Kishon Vijay Abraham I
2014-05-06 13:40 ` Dan Murphy
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=53721D7F.9070200@ti.com \
--to=kishon@ti$(echo .)com \
--cc=linux-arm-kernel@lists$(echo .)infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox