public inbox for linux-arm-kernel@lists.infradead.org 
 help / color / mirror / Atom feed
From: swarren@wwwdotorg•org (Stephen Warren)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v1 5/9] of: Add NVIDIA Tegra XHCI controller binding
Date: Wed, 25 Jun 2014 17:13:10 -0600	[thread overview]
Message-ID: <53AB5786.8090904@wwwdotorg.org> (raw)
In-Reply-To: <CAL1qeaG=nLxDHrsVuuL9c-JdKB+TrNN785+8v=hb0MAFJ=5juw@mail.gmail.com>

On 06/25/2014 05:01 PM, Andrew Bresticker wrote:
> On Wed, Jun 25, 2014 at 2:52 PM, Stephen Warren <swarren@wwwdotorg•org> wrote:
>> On 06/18/2014 12:16 AM, Andrew Bresticker wrote:
>>> Add device-tree binding documentation for the XHCI controller present
>>> on Tegra124 and later SoCs.
>>
>>> diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xhci.txt
>>
>>> +Required properties:
>>> +--------------------
>>
>>> + - clock-names: Must include the following entries:
>>> +    - xusb_host
>>> +    - xusb_falcon_src
>>> +    - xusb_ss
>>> +    - xusb_ss_src
>>> +    - xusb_hs_src
>>> +    - xusb_fs_src
>>> +    - pll_u_480m
>>> +    - clk_m
>>> +    - pll_e
>>
>>> + - reset-names: Must include the following entries:
>>> +   - xusb_host
>>> +   - xusb_ss
>>
>> Usually the CAR has a reset control for each clock. So, I would expect
>> as many entries in reset-names as in clock-names. Even if the SW doesn't
>> currently touch all the reset lines, we should make sure the binding
>> requires them to be present so that any DT will contain the entries if
>> they're ever needed in the future.
> 
> The xusb_{falcon,host,hs,fs,ss}_src clocks all share the same reset
> bit (143), so I can add a single entry for those.
> 
>> In the CAR documentation, I see "XUSB_DEV" as a clock/reset bit. Is that
>> missing from the list above?
> 
> This is used when XUSB is in device mode, which the driver does not
> support.  I can add those clocks here though if you want.

That'd be a good idea. That way, the DT doesn't have to change later.

>>> +Optional properties:
>>
>>> + - s1p05v-supply: 1.05V supply regulator.
>>> + - s1p8v-supply: 1.8V supply regulator.
>>> + - s3p3v-supply: 3.3V supply regulator.
>>
>> What are those supplies for? I would have expected any input to the SoC
>> to have a name that described its purpose, and the pins and DT
>> properties would be named to match.
> 
> I *think* this what they are from looking at the schematic, but I'll
> have to ask around:
>  - s1p05v: avddio_pex, dvddio_pex, and maybe avdd_pll_erefe
>  - s1p8v: avdd_pll_utmip
>  - s3p3v: avdd_usb, hvdd_pex, hvdd_pex_pll_e
> Should these be separated out as they are for PCIe?

Yes, I think they should be separated. I wonder if the supplies for PCIe
shouldn't have been added to the XUSB padctrl rather than PCIe node
though? It probably doesn't matter much either way.

  reply	other threads:[~2014-06-25 23:13 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-18  6:16 [PATCH v1 0/9] Tegra XHCI support Andrew Bresticker
2014-06-18  6:16 ` [PATCH v1 1/9] of: Add NVIDIA Tegra XUSB mailbox binding Andrew Bresticker
2014-06-25 21:42   ` Stephen Warren
2014-06-25 22:37     ` Andrew Bresticker
2014-06-25 23:00       ` Stephen Warren
2014-06-18  6:16 ` [PATCH v1 2/9] mailbox: Add NVIDIA Tegra XUSB mailbox driver Andrew Bresticker
2014-06-25 22:02   ` Stephen Warren
2014-06-25 23:07     ` Andrew Bresticker
2014-06-18  6:16 ` [PATCH v1 3/9] of: Update Tegra XUSB pad controller binding for USB Andrew Bresticker
2014-06-25 21:46   ` Stephen Warren
2014-06-25 22:25     ` Andrew Bresticker
2014-06-26 20:00       ` Stephen Warren
2014-06-18  6:16 ` [PATCH v1 4/9] pinctrl: tegra-xusb: Add USB PHY support Andrew Bresticker
2014-06-25 22:12   ` Stephen Warren
2014-06-25 23:30     ` Andrew Bresticker
2014-06-26 18:08       ` Stephen Warren
2014-06-27 21:22         ` Andrew Bresticker
2014-06-27 15:00       ` Felipe Balbi
2014-06-27 16:05         ` Stephen Warren
2014-06-18  6:16 ` [PATCH v1 5/9] of: Add NVIDIA Tegra XHCI controller binding Andrew Bresticker
2014-06-25 21:52   ` Stephen Warren
2014-06-25 23:01     ` Andrew Bresticker
2014-06-25 23:13       ` Stephen Warren [this message]
2014-06-25 21:54   ` Stephen Warren
2014-06-25 23:02     ` Andrew Bresticker
2014-06-25 23:14       ` Stephen Warren
2014-06-18  6:16 ` [PATCH v1 6/9] usb: xhci: Add NVIDIA Tegra XHCI host-controller driver Andrew Bresticker
2014-06-20 16:58   ` Julius Werner
2014-07-08 21:52     ` Andrew Bresticker
2014-07-09 14:08       ` Alan Stern
2014-07-10 10:40         ` Arnd Bergmann
2014-06-25 22:37   ` Stephen Warren
2014-06-26  0:06     ` Andrew Bresticker
2014-06-26 18:07       ` Stephen Warren
2014-06-27 21:19         ` Andrew Bresticker
2014-06-27 22:01           ` Stephen Warren
2014-06-18  6:16 ` [PATCH v1 7/9] ARM: tegra: Add Tegra124 XUSB mailbox and XHCI controller Andrew Bresticker
2014-06-18  6:16 ` [PATCH v1 8/9] ARM: tegra: jetson-tk1: Add XHCI support Andrew Bresticker
2014-06-18  6:16 ` [PATCH v1 9/9] ARM: tegra: venice2: " Andrew Bresticker

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=53AB5786.8090904@wwwdotorg.org \
    --to=swarren@wwwdotorg$(echo .)org \
    --cc=linux-arm-kernel@lists$(echo .)infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox