From: santosh.shilimkar@ti•com (Santosh Shilimkar)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 0/3] ARM: mvebu: disable I/O coherency on !SMP
Date: Thu, 17 Jul 2014 12:18:06 -0400 [thread overview]
Message-ID: <53C7F73E.1020901@ti.com> (raw)
In-Reply-To: <20140717161010.GY21766@n2100.arm.linux.org.uk>
On Thursday 17 July 2014 12:10 PM, Russell King - ARM Linux wrote:
> On Thu, Jul 17, 2014 at 12:04:26PM -0400, Santosh Shilimkar wrote:
>> Thanks for spotting it RMK. Will have a loot at it.
>
> I already have this for it - which includes a lot more comments on the
> code (some in anticipation of the reply from the architecture people.)
> The first hunk alone should fix the spotted problem.
>
Cool. The alignment fix was easy but I was more worried about the
other part. Thanks for the those additional comments.
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index ab14b79b03f0..917aabd6b2dc 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -1406,8 +1406,8 @@ void __init early_paging_init(const struct machine_desc *mdesc,
> return;
>
> /* remap kernel code and data */
> - map_start = init_mm.start_code;
> - map_end = init_mm.brk;
> + map_start = init_mm.start_code & PMD_MASK;
> + map_end = ALIGN(init_mm.brk, PMD_SIZE);
>
> /* get a handle on things... */
> pgd0 = pgd_offset_k(0);
> @@ -1434,23 +1434,60 @@ void __init early_paging_init(const struct machine_desc *mdesc,
> dsb(ishst);
> isb();
>
> - /* remap level 1 table */
> + /*
> + * WARNING: This code is not architecturally compliant: we modify
> + * the mappings in-place, indeed while they are in use by this
> + * very same code.
> + *
> + * Even modifying the mappings in a separate page table does
> + * not resolve this.
> + *
> + * The architecture strongly recommends that when a mapping is
> + * changed, that it is changed by first going via an invalid
> + * mapping and back to the new mapping. This is to ensure
> + * that no TLB conflicts (caused by the TLB having more than
> + * one TLB entry match a translation) can occur.
> + */
> +
> + /*
> + * Remap level 1 table. This changes the physical addresses
> + * used to refer to the level 2 page tables to the high
> + * physical address alias, leaving everything else the same.
> + */
> for (i = 0; i < PTRS_PER_PGD; pud0++, i++) {
> set_pud(pud0,
> __pud(__pa(pmd0) | PMD_TYPE_TABLE | L_PGD_SWAPPER));
> pmd0 += PTRS_PER_PMD;
> }
>
> - /* remap pmds for kernel mapping */
> - phys = __pa(map_start) & PMD_MASK;
> + /*
> + * Remap the level 2 table, pointing the mappings at the high
> + * physical address alias of these pages.
> + */
> + phys = __pa(map_start);
> do {
> *pmdk++ = __pmd(phys | pmdprot);
> phys += PMD_SIZE;
> } while (phys < map_end);
>
> + /*
> + * Ensure that the above updates are flushed out of the cache.
> + * This is not strictly correct; on a system where the caches
> + * are coherent with each other, but the MMU page table walks
> + * may not be coherent, flush_cache_all() may be a no-op, and
> + * this will fail.
> + */
> flush_cache_all();
> +
> + /*
> + * Re-write the TTBR values to point them at the high physical
> + * alias of the page tables. We expect __va() will work on
> + * cpu_get_pgd(), which returns the value of TTBR0.
> + */
> cpu_switch_mm(pgd0, &init_mm);
> cpu_set_ttbr(1, __pa(pgd0) + TTBR1_OFFSET);
> +
> + /* Finally flush any stale TLB values. */
> local_flush_bp_all();
> local_flush_tlb_all();
> }
>
>
next prev parent reply other threads:[~2014-07-17 16:18 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-02 16:21 [PATCH 0/3] ARM: mvebu: disable I/O coherency on !SMP Thomas Petazzoni
2014-07-02 16:21 ` [PATCH 1/3] ARM: mvebu: make the coherency_ll.S functions work with no coherency fabric Thomas Petazzoni
2014-07-02 16:21 ` [PATCH 2/3] ARM: mvebu: disable I/O coherency on non-SMP situations on Armada 370/XP Thomas Petazzoni
2014-07-02 16:21 ` [PATCH 3/3] ARM: mvebu: add missing of_node_put() call in coherency.c Thomas Petazzoni
2014-07-02 16:27 ` [PATCH 0/3] ARM: mvebu: disable I/O coherency on !SMP Andrew Lunn
2014-07-02 16:41 ` Russell King - ARM Linux
2014-07-02 17:18 ` Thomas Petazzoni
2014-07-02 17:58 ` Russell King - ARM Linux
2014-07-02 20:28 ` Thomas Petazzoni
2014-07-02 21:33 ` Russell King - ARM Linux
2014-07-02 21:50 ` Thomas Petazzoni
2014-07-17 8:24 ` Thomas Petazzoni
2014-07-17 8:33 ` Russell King - ARM Linux
2014-07-17 8:45 ` Thomas Petazzoni
2014-07-17 10:27 ` Russell King - ARM Linux
2014-07-17 10:16 ` Russell King - ARM Linux
2014-07-17 12:39 ` Arnd Bergmann
2014-07-17 13:12 ` Russell King - ARM Linux
2014-07-17 14:27 ` Will Deacon
2014-07-17 14:40 ` Arnd Bergmann
2014-07-17 15:34 ` Russell King - ARM Linux
2014-07-17 15:53 ` Arnd Bergmann
2014-07-17 16:04 ` Santosh Shilimkar
2014-07-17 16:10 ` Russell King - ARM Linux
2014-07-17 16:18 ` Santosh Shilimkar [this message]
2014-07-28 17:46 ` Will Deacon
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