* [PATCH v2 0/3] Add clock binding id for rk3288
@ 2014-09-24 15:33 Kever Yang
2014-09-24 15:33 ` [PATCH v2 2/3] clk: rockchip: use the clock id for nodes init Kever Yang
2014-09-24 15:33 ` [PATCH v2 3/3] clk: rockchip: add clock node in PD_VIDEO Kever Yang
0 siblings, 2 replies; 6+ messages in thread
From: Kever Yang @ 2014-09-24 15:33 UTC (permalink / raw)
To: linux-arm-kernel
This patch add some clock binding id for different modules
that under development and going to send upstream.
This patch also add the clock node in PD_VIDEO.
Changes in v2:
- split into two patches of add clock node in PD_VIDEO and
use new defined clock ID
Kever Yang (3):
clk: rockchip: add some needed clock binding id for rk3288
clk: rockchip: use the clock id for nodes init
clk: rockchip: add clock node in PD_VIDEO
drivers/clk/rockchip/clk-rk3288.c | 79 +++++++++++++++++++---------------
include/dt-bindings/clock/rk3288-cru.h | 38 +++++++++++++++-
2 files changed, 82 insertions(+), 35 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 2/3] clk: rockchip: use the clock id for nodes init
2014-09-24 15:33 [PATCH v2 0/3] Add clock binding id for rk3288 Kever Yang
@ 2014-09-24 15:33 ` Kever Yang
2014-09-24 17:57 ` Doug Anderson
2014-09-24 15:33 ` [PATCH v2 3/3] clk: rockchip: add clock node in PD_VIDEO Kever Yang
1 sibling, 1 reply; 6+ messages in thread
From: Kever Yang @ 2014-09-24 15:33 UTC (permalink / raw)
To: linux-arm-kernel
This patch use the new defined clock ID to initial the clock nodes.
Signed-off-by: Kever Yang <kever.yang@rock-chips•com>
Reviewed-by: Heiko Stuebner <heiko@sntech•de>
---
Changes in v2:
- split into two patches of add clock node in PD_VIDEO and
use new defined clock ID
drivers/clk/rockchip/clk-rk3288.c | 68 +++++++++++++++++++--------------------
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 8ea885b..d691a56 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -219,12 +219,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
DIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0,
RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
- GATE(0, "aclk_cpu", "aclk_cpu_pre", 0,
+ GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,
RK3288_CLKGATE_CON(0), 3, GFLAGS),
- COMPOSITE_NOMUX(0, "pclk_cpu", "aclk_cpu_pre", 0,
+ COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", 0,
RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
RK3288_CLKGATE_CON(0), 5, GFLAGS),
- COMPOSITE_NOMUX_DIVTBL(0, "hclk_cpu", "aclk_cpu_pre", 0,
+ COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", 0,
RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
RK3288_CLKGATE_CON(0), 4, GFLAGS),
GATE(0, "c2c_host", "aclk_cpu_src", 0,
@@ -309,7 +309,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 5, GFLAGS),
- COMPOSITE(0, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
+ COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 4, GFLAGS),
@@ -320,35 +320,35 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKGATE_CON(3), 3, GFLAGS),
- COMPOSITE_NODIV(0, "sclk_edp_24m", mux_edp_24m_p, 0,
+ COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
RK3288_CLKGATE_CON(3), 12, GFLAGS),
- COMPOSITE(0, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 13, GFLAGS),
- COMPOSITE(0, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 14, GFLAGS),
- COMPOSITE(0, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 15, GFLAGS),
- GATE(0, "sclk_hdmi_hdcp", "xin24m", 0,
+ GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
RK3288_CLKGATE_CON(5), 12, GFLAGS),
- GATE(0, "sclk_hdmi_cec", "xin32k", 0,
+ GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
RK3288_CLKGATE_CON(5), 11, GFLAGS),
- COMPOSITE(0, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 13, GFLAGS),
- DIV(0, "hclk_hevc", "aclk_hevc", 0,
+ DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
- COMPOSITE(0, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 14, GFLAGS),
- COMPOSITE(0, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 15, GFLAGS),
@@ -371,13 +371,13 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, 0,
RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(2), 0, GFLAGS),
- COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_src", 0,
+ COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK3288_CLKGATE_CON(2), 3, GFLAGS),
- COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_src", 0,
+ COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK3288_CLKGATE_CON(2), 2, GFLAGS),
- GATE(0, "aclk_peri", "aclk_peri_src", 0,
+ GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
RK3288_CLKGATE_CON(2), 1, GFLAGS),
/*
@@ -643,34 +643,34 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
- GATE(0, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS),
- GATE(0, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),
- GATE(0, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
+ GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS),
+ GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),
+ GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
- GATE(0, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS),
- GATE(0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
- GATE(0, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
- GATE(0, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
- GATE(0, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
- GATE(0, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS),
- GATE(0, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
- GATE(0, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS),
+ GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS),
+ GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
+ GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
+ GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
+ GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
+ GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS),
+ GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
+ GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS),
/* aclk_vio0 gates */
GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
- GATE(0, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
- GATE(0, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),
- GATE(0, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
+ GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
+ GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),
+ GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
/* aclk_vio1 gates */
GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
- GATE(0, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
- GATE(0, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),
+ GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
+ GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),
/* aclk_rga_pre gates */
GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
- GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),
+ GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),
/*
* Other ungrouped clocks.
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 3/3] clk: rockchip: add clock node in PD_VIDEO
2014-09-24 15:33 [PATCH v2 0/3] Add clock binding id for rk3288 Kever Yang
2014-09-24 15:33 ` [PATCH v2 2/3] clk: rockchip: use the clock id for nodes init Kever Yang
@ 2014-09-24 15:33 ` Kever Yang
2014-09-24 19:48 ` Doug Anderson
1 sibling, 1 reply; 6+ messages in thread
From: Kever Yang @ 2014-09-24 15:33 UTC (permalink / raw)
To: linux-arm-kernel
This patch add the clock node in PD_VIDEO
Signed-off-by: Kever Yang <kever.yang@rock-chips•com>
Reviewed-by: Heiko Stuebner <heiko@sntech•de>
---
Changes in v2:
- split out the patch
drivers/clk/rockchip/clk-rk3288.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index d691a56..2cfcfb6 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -296,6 +296,17 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 11, GFLAGS),
+ /*
+ * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system,
+ * so we ignore the mux and make clocks nodes as following,
+ * NOTE THAT hclk_vcodec is fix div by 4 from aclk_vcodec_pre.
+ */
+ GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0,
+ RK3288_CLKGATE_CON(9), 0, GFLAGS),
+ GATE(0, "hclk_vcodec_pre", "aclk_vdpu", 0,
+ RK3288_CLKGATE_CON(3), 10, GFLAGS),
+ GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
+ RK3288_CLKGATE_CON(9), 1, GFLAGS),
COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/3] clk: rockchip: use the clock id for nodes init
2014-09-24 15:33 ` [PATCH v2 2/3] clk: rockchip: use the clock id for nodes init Kever Yang
@ 2014-09-24 17:57 ` Doug Anderson
0 siblings, 0 replies; 6+ messages in thread
From: Doug Anderson @ 2014-09-24 17:57 UTC (permalink / raw)
To: linux-arm-kernel
Kever,
On Wed, Sep 24, 2014 at 8:33 AM, Kever Yang <kever.yang@rock-chips•com> wrote:
> This patch use the new defined clock ID to initial the clock nodes.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips•com>
> Reviewed-by: Heiko Stuebner <heiko@sntech•de>
> ---
>
> Changes in v2:
> - split into two patches of add clock node in PD_VIDEO and
> use new defined clock ID
>
> drivers/clk/rockchip/clk-rk3288.c | 68 +++++++++++++++++++--------------------
> 1 file changed, 34 insertions(+), 34 deletions(-)
Reviewed-by: Doug Anderson <dianders@chromium•org>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 3/3] clk: rockchip: add clock node in PD_VIDEO
2014-09-24 15:33 ` [PATCH v2 3/3] clk: rockchip: add clock node in PD_VIDEO Kever Yang
@ 2014-09-24 19:48 ` Doug Anderson
2014-09-25 1:28 ` Kever Yang
0 siblings, 1 reply; 6+ messages in thread
From: Doug Anderson @ 2014-09-24 19:48 UTC (permalink / raw)
To: linux-arm-kernel
Kever,
On Wed, Sep 24, 2014 at 8:33 AM, Kever Yang <kever.yang@rock-chips•com> wrote:
> This patch add the clock node in PD_VIDEO
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips•com>
> Reviewed-by: Heiko Stuebner <heiko@sntech•de>
> ---
>
> Changes in v2:
> - split out the patch
>
> drivers/clk/rockchip/clk-rk3288.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
> index d691a56..2cfcfb6 100644
> --- a/drivers/clk/rockchip/clk-rk3288.c
> +++ b/drivers/clk/rockchip/clk-rk3288.c
> @@ -296,6 +296,17 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
> COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
> RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
> RK3288_CLKGATE_CON(3), 11, GFLAGS),
> + /*
> + * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system,
> + * so we ignore the mux and make clocks nodes as following,
I guess we can't add the mux for now because it's in the GRF and not
in the clock area and the current clock tables don't have support for
that. I guess that OK for now, but eventually we should probably add
it in.
> + * NOTE THAT hclk_vcodec is fix div by 4 from aclk_vcodec_pre.
Typo: from "aclk_vcodec_pre" or from "hclk_vcodec_pre"?
> + */
> + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0,
> + RK3288_CLKGATE_CON(9), 0, GFLAGS),
> + GATE(0, "hclk_vcodec_pre", "aclk_vdpu", 0,
> + RK3288_CLKGATE_CON(3), 10, GFLAGS),
> + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
> + RK3288_CLKGATE_CON(9), 1, GFLAGS),
Shouldn't there be a fixed "/ 4" clock somewhere in here? That way
the clock rate will be reported correctly?
I guess the cleanest would be to add support to rockchip/clk.c to call
clk_register_fixed_factor() somehow. I guess I'll leave it to you and
Heiko to decide what you want to do here.
-Doug
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 3/3] clk: rockchip: add clock node in PD_VIDEO
2014-09-24 19:48 ` Doug Anderson
@ 2014-09-25 1:28 ` Kever Yang
0 siblings, 0 replies; 6+ messages in thread
From: Kever Yang @ 2014-09-25 1:28 UTC (permalink / raw)
To: linux-arm-kernel
Hi Doug,
On 09/25/2014 03:48 AM, Doug Anderson wrote:
> Kever,
>
> On Wed, Sep 24, 2014 at 8:33 AM, Kever Yang <kever.yang@rock-chips•com> wrote:
>> This patch add the clock node in PD_VIDEO
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips•com>
>> Reviewed-by: Heiko Stuebner <heiko@sntech•de>
>> ---
>>
>> Changes in v2:
>> - split out the patch
>>
>> drivers/clk/rockchip/clk-rk3288.c | 11 +++++++++++
>> 1 file changed, 11 insertions(+)
>>
>> diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
>> index d691a56..2cfcfb6 100644
>> --- a/drivers/clk/rockchip/clk-rk3288.c
>> +++ b/drivers/clk/rockchip/clk-rk3288.c
>> @@ -296,6 +296,17 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
>> COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
>> RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
>> RK3288_CLKGATE_CON(3), 11, GFLAGS),
>> + /*
>> + * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system,
>> + * so we ignore the mux and make clocks nodes as following,
> I guess we can't add the mux for now because it's in the GRF and not
> in the clock area and the current clock tables don't have support for
> that. I guess that OK for now, but eventually we should probably add
> it in.
The mux setting moved to GRF because it switch the clock source and some
other
controller logic.
The VCODEC can be used as encoder or decoder, we use it as decoder by
default,
so I guess we can ignore the decoder part before the clock module can
handle this.
>
>
>> + * NOTE THAT hclk_vcodec is fix div by 4 from aclk_vcodec_pre.
> Typo: from "aclk_vcodec_pre" or from "hclk_vcodec_pre"?
hclk_vcodec_pre is /4 from aclk_vcodec_pre, and hclk_vcodec has a gate
from hclk_vcodec_pre.
I should fix this.
>
>> + */
>> + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0,
>> + RK3288_CLKGATE_CON(9), 0, GFLAGS),
>> + GATE(0, "hclk_vcodec_pre", "aclk_vdpu", 0,
>> + RK3288_CLKGATE_CON(3), 10, GFLAGS),
>> + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
>> + RK3288_CLKGATE_CON(9), 1, GFLAGS),
> Shouldn't there be a fixed "/ 4" clock somewhere in here? That way
> the clock rate will be reported correctly?
>
> I guess the cleanest would be to add support to rockchip/clk.c to call
> clk_register_fixed_factor() somehow. I guess I'll leave it to you and
> Heiko to decide what you want to do here.
There is a fixed "/4" that not add to this tree, which makes we get a 4
times
of real rate when we get the HCLK_VCODEC, that is why I write a commend
with "NOTE THAT" before.
I know there is a clk_register_fixed_factor(), but I'm not sure how to use
it here, this is a table.
I'll try to add the clk_register_fixed_factor() today.
-Kever
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2014-09-25 1:28 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-09-24 15:33 [PATCH v2 0/3] Add clock binding id for rk3288 Kever Yang
2014-09-24 15:33 ` [PATCH v2 2/3] clk: rockchip: use the clock id for nodes init Kever Yang
2014-09-24 17:57 ` Doug Anderson
2014-09-24 15:33 ` [PATCH v2 3/3] clk: rockchip: add clock node in PD_VIDEO Kever Yang
2014-09-24 19:48 ` Doug Anderson
2014-09-25 1:28 ` Kever Yang
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