From: gregory.clement@free-electrons•com (Gregory CLEMENT)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 12/17] ARM: mvebu: Armada XP GP specific suspend/resume code
Date: Mon, 10 Nov 2014 14:53:38 +0100 [thread overview]
Message-ID: <5460C362.2090802@free-electrons.com> (raw)
In-Reply-To: <1414151970-6626-13-git-send-email-thomas.petazzoni@free-electrons.com>
Hi Thomas,
[...]
> +#include "common.h"
> +
> +#define ARMADA_XP_GP_PIC_NR_GPIOS 3
> +
> +static void __iomem *gpio_ctrl;
> +static int pic_gpios[ARMADA_XP_GP_PIC_NR_GPIOS];
> +static int pic_raw_gpios[ARMADA_XP_GP_PIC_NR_GPIOS];
> +
> +static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd)
> +{
> + u32 reg, ackcmd;
> + int i;
> +
> + /* Put 001 as value on the GPIOs */
> + reg = readl(gpio_ctrl);
> + for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)
> + reg &= ~BIT(pic_raw_gpios[i]);
> + reg |= BIT(pic_raw_gpios[0]);
> + writel(reg, gpio_ctrl);
> +
> + /* Prepare writing 111 to the GPIOs */
> + ackcmd = readl(gpio_ctrl);
> + for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)
> + ackcmd |= BIT(pic_raw_gpios[i]);
> +
> + /* Wait a while */
> + mdelay(250);
> +
> + asm volatile (
> + /* Align to a cache line */
> + ".balign 32\n\t"
> +
> + /* Enter self refresh */
> + "str %[srcmd], [%[sdram_reg]]\n\t"
> +
> + /* Wait 100 cycles for DDR to enter self refresh */
> + "1: subs r1, r1, #1\n\t"
I should miss something obvious, but I don't see where you load 100 in
the r1 register. According to your comment and the code, you remove 1 from
r1 until it reaches 0, so I expected that just before you have loaded 100 in r1.
Thanks,
Gregory
> + "bne 1b\n\t"
> +
> + /* Issue the command ACK */
> + "str %[ackcmd], [%[gpio_ctrl]]\n\t"
> +
> + /* Trap the processor */
> + "b .\n\t"
> + : : [srcmd] "r" (srcmd), [sdram_reg] "r" (sdram_reg),
> + [ackcmd] "r" (ackcmd), [gpio_ctrl] "r" (gpio_ctrl) : "r1");
> +}
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
next prev parent reply other threads:[~2014-11-10 13:53 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-24 11:59 [PATCH 00/17] Suspend to RAM support for Armada XP Thomas Petazzoni
2014-10-24 11:59 ` [PATCH 01/17] Documentation: dt-bindings: minimal documentation for MVEBU SDRAM controller Thomas Petazzoni
2014-11-03 17:05 ` Gregory CLEMENT
2014-10-24 11:59 ` [PATCH 02/17] ARM: mvebu: enable strex backoff delay Thomas Petazzoni
2014-11-03 17:08 ` Gregory CLEMENT
2014-10-24 11:59 ` [PATCH 03/17] irqchip: irq-armada-370-xp: use proper return value for ->set_affinity() Thomas Petazzoni
2014-11-03 17:20 ` Gregory CLEMENT
2014-11-07 4:09 ` Jason Cooper
2014-10-24 11:59 ` [PATCH 04/17] irqchip: irq-armada-370-xp: suspend/resume support Thomas Petazzoni
2014-11-03 17:38 ` Gregory CLEMENT
2014-11-13 16:32 ` Thomas Petazzoni
2014-10-24 11:59 ` [PATCH 05/17] clocksource: time-armada-370-xp: add " Thomas Petazzoni
2014-11-03 17:45 ` Gregory CLEMENT
2014-10-24 11:59 ` [PATCH 06/17] gpio: mvebu: " Thomas Petazzoni
2014-10-24 16:30 ` David Cohen
2014-10-24 20:45 ` Andrew Lunn
2014-10-27 5:27 ` Alexandre Courbot
2014-10-27 17:45 ` David Cohen
2014-10-31 7:00 ` Linus Walleij
2014-10-31 7:52 ` Gregory CLEMENT
2014-10-31 8:14 ` Thomas Petazzoni
2014-11-03 13:26 ` Linus Walleij
2014-11-03 13:29 ` Linus Walleij
2014-11-03 17:53 ` Gregory CLEMENT
2014-11-03 21:21 ` Thomas Petazzoni
2014-10-24 11:59 ` [PATCH 07/17] bus: mvebu-mbus: " Thomas Petazzoni
2014-11-03 18:08 ` Gregory CLEMENT
2014-11-03 21:20 ` Thomas Petazzoni
2014-10-24 11:59 ` [PATCH 08/17] bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration Thomas Petazzoni
2014-11-04 9:17 ` Gregory CLEMENT
2014-10-24 11:59 ` [PATCH 09/17] clk: mvebu: add suspend/resume for gatable clocks Thomas Petazzoni
2014-11-04 9:32 ` Gregory CLEMENT
2014-10-24 11:59 ` [PATCH 10/17] ARM: mvebu: implement suspend/resume support for Armada XP Thomas Petazzoni
2014-11-04 10:00 ` Gregory CLEMENT
2014-11-13 17:00 ` Thomas Petazzoni
2014-10-24 11:59 ` [PATCH 11/17] ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume Thomas Petazzoni
2014-11-04 10:09 ` Gregory CLEMENT
2014-10-24 11:59 ` [PATCH 12/17] ARM: mvebu: Armada XP GP specific suspend/resume code Thomas Petazzoni
2014-10-24 14:20 ` Andrew Lunn
2014-10-24 14:28 ` Thomas Petazzoni
2014-10-24 14:51 ` Andrew Lunn
2014-10-27 12:51 ` Thomas Petazzoni
2014-10-27 14:19 ` Andrew Lunn
2014-10-27 14:40 ` Thomas Petazzoni
2014-10-27 14:59 ` Andrew Lunn
2014-10-27 15:12 ` Thomas Petazzoni
2014-10-27 15:15 ` Andrew Lunn
2014-11-10 13:53 ` Gregory CLEMENT [this message]
2014-10-24 11:59 ` [PATCH 13/17] ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume Thomas Petazzoni
2014-11-10 14:05 ` Gregory CLEMENT
2014-10-24 11:59 ` [PATCH 14/17] ARM: mvebu: synchronize secondary CPU clocks on resume Thomas Petazzoni
2014-11-10 14:12 ` Gregory CLEMENT
2014-10-24 11:59 ` [PATCH 15/17] ARM: mvebu: add suspend/resume DT information for Armada XP GP Thomas Petazzoni
2014-11-10 14:14 ` Gregory CLEMENT
2014-10-24 11:59 ` [PATCH 16/17] ARM: mvebu: adjust mbus controller description on Armada 370/XP Thomas Petazzoni
2014-11-10 14:15 ` Gregory CLEMENT
2014-10-24 11:59 ` [PATCH 17/17] ARM: mvebu: add SDRAM controller description for Armada XP Thomas Petazzoni
2014-11-10 14:25 ` Gregory CLEMENT
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