From: ddaney@caviumnetworks•com (David Daney)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 3/3] PCI: generic: Add support for Cavium ThunderX PCIe root complexes.
Date: Tue, 22 Sep 2015 09:56:52 -0700 [thread overview]
Message-ID: <56018854.1030106@caviumnetworks.com> (raw)
In-Reply-To: <20150922164012.GA3692@red-moon>
On 09/22/2015 09:40 AM, Lorenzo Pieralisi wrote:
> On Tue, Sep 22, 2015 at 05:13:45PM +0100, David Daney wrote:
>> On 09/22/2015 09:05 AM, Lorenzo Pieralisi wrote:
>>> On Thu, Sep 17, 2015 at 11:41:34PM +0100, David Daney wrote:
>
> [...]
>
>>>> Properties of the host controller node:
>>>>
>>>> -- compatible : Must be "pci-host-cam-generic" or "pci-host-ecam-generic"
>>>> - depending on the layout of configuration space (CAM vs
>>>> - ECAM respectively).
>>>> +- compatible : One of the following with bus:devfn:reg mapped to the
>>>> + PCI config space address window in the bit positions shown:
>>>> + "pci-host-cam-generic" -- 'CAM' bits 16:8:0
>>>> + "pci-host-ecam-generic" -- 'ECAM' bits 20:12:0
>>>> + "cavium,pci-host-thunder-pem" -- bits 24:16:0
>>>
>>> To me that's ECAM left shifted by 4. Is not it just a matter of defining
>>> config space base address (ie reg property) differently ?
>>
>> No.
>>
>> That's like saying ECAM is just CAM shifted by 4, can't we just specify
>> the "reg" differently.
>
> Ok, sorry I was not clear, apologies. I meant to ask if it is something
> that can be configured in your platform and apparently it is not,
No, the hardware cannot be adjusted.
> I worded it wrongly.
OK, I guess I also misunderstood what you were suggesting.
>
>> The "reg" property describes the base of the config space access window.
>> CAM/ECAM/cavium,pci-host-thunder-pem describe how to generate offsets
>> from that base, The offset calculation requires information that is not
>> present in the "reg" property, it is enumerated in the various
>> "compatible" values listed above.
>
> Agreed, this also forces you to map in more virtual address space for
> a given bus, right ?
Yes. It takes a full 32-bits of address space to have access to all PCI
buses on the root complex.
> I am also a bit worried about how we can make this
> work with ACPI, where MCFG accessors take the bus and devfn shifts for
> granted (ie ECAM specs), so I asked.
If ACPI is not flexible enough to describe actual hardware, it will
either have to be enhanced, or not used.
>
> Thanks,
> Lorenzo
>
>>
>> David Daney
>>
>>>
>>> Lorenzo
>>>
>>>>
>>>> - device_type : Must be "pci".
>>>>
>>>> diff --git a/drivers/pci/host/pci-host-generic.c b/drivers/pci/host/pci-host-generic.c
>>>> index e364232..e1d8d5b 100644
>>>> --- a/drivers/pci/host/pci-host-generic.c
>>>> +++ b/drivers/pci/host/pci-host-generic.c
>>>> @@ -91,6 +91,32 @@ static struct gen_pci_cfg_bus_ops gen_pci_cfg_ecam_bus_ops = {
>>>> }
>>>> };
>>>>
>>>> +static void __iomem *gen_pci_map_cfg_bus_thunder_pem(struct pci_bus *bus,
>>>> + unsigned int devfn,
>>>> + int where)
>>>> +{
>>>> + struct gen_pci *pci = bus->sysdata;
>>>> + resource_size_t idx = bus->number - pci->cfg.bus_range->start;
>>>> +
>>>> + /*
>>>> + * Thunder PEM is a PCIe RC, but without a root bridge. On
>>>> + * the primary bus, ignore accesses for devices other than
>>>> + * the first device.
>>>> + */
>>>> + if (idx == 0 && (devfn & ~7u))
>>>> + return NULL;
>>>> + return pci->cfg.win[idx] + ((devfn << 16) | where);
>>>> +}
>>>> +
>>>> +static struct gen_pci_cfg_bus_ops gen_pci_cfg_thunder_pem_bus_ops = {
>>>> + .bus_shift = 24,
>>>> + .ops = {
>>>> + .map_bus = gen_pci_map_cfg_bus_thunder_pem,
>>>> + .read = pci_generic_config_read,
>>>> + .write = pci_generic_config_write,
>>>> + }
>>>> +};
>>>> +
>>>> static const struct of_device_id gen_pci_of_match[] = {
>>>> { .compatible = "pci-host-cam-generic",
>>>> .data = &gen_pci_cfg_cam_bus_ops },
>>>> @@ -98,6 +124,9 @@ static const struct of_device_id gen_pci_of_match[] = {
>>>> { .compatible = "pci-host-ecam-generic",
>>>> .data = &gen_pci_cfg_ecam_bus_ops },
>>>>
>>>> + { .compatible = "cavium,pci-host-thunder-pem",
>>>> + .data = &gen_pci_cfg_thunder_pem_bus_ops },
>>>> +
>>>> { },
>>>> };
>>>> MODULE_DEVICE_TABLE(of, gen_pci_of_match);
>>>> --
>>>> 1.9.1
>>>>
>>>> --
>>>> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
>>>> the body of a message to majordomo at vger.kernel.org
>>>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>>>
>>
next prev parent reply other threads:[~2015-09-22 16:56 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-17 22:41 [PATCH 0/3] PCI: Add support for Cavium ThunderX RC and on-SoC devices David Daney
2015-09-17 22:41 ` [PATCH 1/3] PCI: Allow quirks to override SRIOV BARs David Daney
2015-09-17 22:41 ` [PATCH 2/3] PCI: Add quirks for devices found on Cavium ThunderX SoCs David Daney
2015-09-18 7:19 ` Arnd Bergmann
2015-09-18 17:00 ` David Daney
2015-09-18 19:45 ` Arnd Bergmann
2015-09-19 1:00 ` David Daney
2015-09-22 13:19 ` Bjorn Helgaas
2015-09-23 16:24 ` David Daney
2015-09-22 15:39 ` Lorenzo Pieralisi
2015-09-22 19:33 ` Arnd Bergmann
2015-09-17 22:41 ` [PATCH 3/3] PCI: generic: Add support for Cavium ThunderX PCIe root complexes David Daney
2015-09-22 16:05 ` Lorenzo Pieralisi
2015-09-22 16:13 ` David Daney
2015-09-22 16:40 ` Lorenzo Pieralisi
2015-09-22 16:56 ` David Daney [this message]
2015-09-22 18:52 ` Will Deacon
2015-09-22 19:02 ` David Daney
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