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From: tanxiaojun@huawei•com (Tan Xiaojun)
To: linux-arm-kernel@lists•infradead.org
Subject: [QUESTION] Arm64: Query L3 cache info via DT
Date: Wed, 28 Dec 2016 11:42:12 +0800	[thread overview]
Message-ID: <58633494.9030708@huawei.com> (raw)

Hi.

I saw you discussed how to achieve querying cache information and tend to implement the external ones(like L3 cache) via DT a few months ago.

http://lists.infradead.org/pipermail/linux-arm-kernel/2016-February/405399.html

Are these implementations progressing? Forgive me to take the liberty to ask, we care about this thing.

If you've already implemented some codes, we can help with testing (in Hisilicon D02, D03, D05) after you send it to the mail-list.

We can try our best to help if there is any difficulty.


Thanks.
Xiaojun.

next             reply	other threads:[~2016-12-28  3:42 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-28  3:42 Tan Xiaojun [this message]
2017-01-04 11:47 ` [QUESTION] Arm64: Query L3 cache info via DT Sudeep Holla
2017-01-05  3:43   ` Tan Xiaojun
2017-01-10  8:50   ` Tan Xiaojun
2017-01-10 10:01     ` Sudeep Holla
2017-01-10 10:54       ` Tan Xiaojun
2017-01-10 11:50         ` Sudeep Holla
2017-01-12  2:26           ` Tan Xiaojun
2017-01-12 18:34     ` Sudeep Holla

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