From: tanxiaojun@huawei•com (Tan Xiaojun)
To: linux-arm-kernel@lists•infradead.org
Subject: [QUESTION] Arm64: Query L3 cache info via DT
Date: Thu, 12 Jan 2017 10:26:02 +0800 [thread overview]
Message-ID: <5876E93A.5090203@huawei.com> (raw)
In-Reply-To: <913e50ac-5040-8a91-539b-136ed7cde1e3@arm.com>
On 2017/1/10 19:50, Sudeep Holla wrote:
>
>
> On 10/01/17 10:54, Tan Xiaojun wrote:
>> On 2017/1/10 18:01, Sudeep Holla wrote:
>>>
>>>
>>> On 10/01/17 08:50, Tan Xiaojun wrote:
>>>> I add this patch, and test in Hisilicon D02/D03. It can work well.
>>>>
>>>> I'm sorry to reply so late. I took some time to debug, because I am not familiar with the code.
>>>>
>>>>> + if (level < of_level) {
>>>>> + /*
>>>>> + * some external caches not specified in CLIDR_EL1
>>>>> + * the information may be available in the device tree
>>>>> + * only unified external caches are considered here
>>>>> + */
>>>>> + level = of_level;
>>>>> + leaves += (of_level - level);
>>>>
>>>> The above two lines need to exchange the location.
>>>>
>>>
>>> Ah crap, sorry for such a silly mistake.
>>> I will post proper patch(es) soon.
>>>
>>
>> OK. Wait for your new patch. ^_^
>>
>
> Thanks, I have posted the patches[1] and Cc-ed you on them. It would be
> good to get Tested-by once you check.
>
OK. I'm glad to do this.
Thanks.
Xiaojun.
next prev parent reply other threads:[~2017-01-12 2:26 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-28 3:42 [QUESTION] Arm64: Query L3 cache info via DT Tan Xiaojun
2017-01-04 11:47 ` Sudeep Holla
2017-01-05 3:43 ` Tan Xiaojun
2017-01-10 8:50 ` Tan Xiaojun
2017-01-10 10:01 ` Sudeep Holla
2017-01-10 10:54 ` Tan Xiaojun
2017-01-10 11:50 ` Sudeep Holla
2017-01-12 2:26 ` Tan Xiaojun [this message]
2017-01-12 18:34 ` Sudeep Holla
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